
==== Front
Heliyon
Heliyon
Heliyon
2405-8440
Elsevier

S2405-8440(24)12786-7
10.1016/j.heliyon.2024.e36755
e36755
Research Article
An event-triggered synchronization strategy for high-precise clock systems with switching topologies
Zhao Hui zhaohui_209@163.com
a⁎
Dai Xuewu b
Zhao Yuan c
a School of Artificial Intelligence, Shenyang University of Technology, Shenyang, 110870, China
b Department of Mathematics, Physics and Electrical Engineering, Northumbria University, NE1 8ST Newcastle upon Tyne, UK
c College of Information Engineering, Dalian University, Dalian, 116622, China
⁎ Corresponding author. zhaohui_209@163.com
26 8 2024
15 9 2024
26 8 2024
10 17 e3675521 5 2024
10 7 2024
21 8 2024
© 2024 The Author(s)
2024
https://creativecommons.org/licenses/by-nc/4.0/ This is an open access article under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
The clock synchronization is a key technology for the reliability of wireless sensor networks (WSN). To reduce the communication burden and address the challenge of clock synchronization for high-precise clock systems in WSN with switching topologies, this paper proposes an event-triggered synchronization strategy for high-precise clock systems. Firstly, based on the concept of offset and skew, the model of whole clock systems is investigated and an event-triggered strategy is proposed for high-precise clock systems with switching topologies. Then, a synchronization strategy for clock systems is presented to achieve clock synchronization with the convergence of clock offset and clock skew. The sufficient condition for the synchronization of high-precise clock systems with switching topologies is obtained. Afterwards, the optimal event-triggered weighting matrices and controller gains are calculated by converting the clock synchronization problem as a solvable optimization problem. Finally, the performance of the proposed clock synchronization method is evaluated by simulations.

Keywords

Clock synchronization
Event-triggered
Clock systems
Switching topologies
==== Body
pmc1 Introduction

With the development of science and technology, the Internet of Things (IoT) have been closely related to human life. Specially, the Industrial Internet of Things (IIoT) have become the common research hotspot in academia and industry fields. As a key technology in IIoT, the industrial wireless sensor networks (WSN) can solve the perception, communication, and control problems of moving plants in industrial environments or plants that cannot be wired in harsh environments [1], [2], [3], [4]. Because industrial systems have strict requirements for real-time and deterministic performance, it is critical to ensure that the devices connected to WSN have high-precise clocks for data acquisition and system control. The clock synchronization means that the sensor and actuator nodes in a network have the same time base and the clocks in WSN should be synchronized. The clock synchronization technology is an important supporting technology of WSN. Many applications of WSN need clock synchronization as the premise. The industrial wireless technology is the continuation of WSN technology. In general, the industrial WSN have higher requirements for real-time and reliability. The high-precise clock synchronization mechanism will play a decisive role in the real-time performance of industrial WSN.

In recent years, the clock synchronization technology has begun to develop rapidly. Scholars from all over the world are actively committed to the research of clock synchronization and have proposed a variety of clock synchronization protocols [5], [6], [7], [8]. From the perspectives of network communication and clock synchronization packet exchange, the clock synchronization can be divided into synchronization protocols based on receiver-receiver and sender-receiver [9], [10]. In the control field, the clock synchronization can be regarded as a consensus problem, and then the appropriate controller is designed for clock synchronization. For example, Jia et al. investigated a disturbance compensation strategy for clock synchronization based on proportional-integral observer [11]. Then with the proposed a zero-pole optimal algorithm, the clock synchronization for a network can be achieved. In reference [12], Wu et al. adopted a layered and distributed control structure to design the global phase and frequency synchronization control scheme for the Kuramoto type oscillator network with random interference in the communication channel.

Due to the high precision of clock synchronization algorithm, the higher requirements are put forward for the reliability of WSN. However, for the high value of clock information in transmission network, it is often subjected to various strong interference and even network attacks. The switching of communication topology is one of the common consequences of strong interference and network attacks. In fact, the switching topologies are often occurred because of fast information exchange and channel fading [13]. The consensus problem of the network with switching topologies has attracted widely attention [14], [15], [16], [17], [18]. For high-precise clock systems, the switching topologies have an important impact on the accuracy of clock synchronization, and even affect whether the clock systems can achieve clock synchronization. Therefore, it is necessary to study clock synchronization under switching topologies, especially when the interference is subjected in WSN. But there exists little research concerned about the clock synchronization problem with switching topologies, which is the first motivation of this paper.

For high-precise clock systems, the transmission of clock information is usually characterized by high frequency. How to save communication resource for realizing the effective use of WSN is one of the problems that needs to be concerned. The event-triggered strategy is a control mode based on preset triggered condition. If a control task meets the triggered condition, an event occurs. In this case, the system executes the triggered task to transfer information between neighbors or update the controller [19], [20], [21]. It can effectively reduce the execution times of control tasks and solve the problem of high frequency communication [22]. In the consensus control for intelligent systems, the control algorithm based on event-triggered mechanism has achieved a lot of results, such as control for autonomous vehicles, high-speed trains, robot systems, and satellite systems, et al. For example, by utilizing CARLA simulator, Zhou et al. [23] proposed an event-triggered scheme for vehicle path tracking with fewer control sequences. In reference [24], a distributed event-based cooperation scheme was investigated for railway trains. Li et al. [25] studied an event-triggered command mechanism for robot manipulators to eliminate the communication burden. Zhao et al. [26] presented a hybrid event-based method for the application of satellite formation problem. However, in the field of clock synchronization, only Jia et al. [27] proposed an event-triggered synchronization scheme for clock systems. The event-triggered synchronization scheme for clock systems still needs to be further studied. To reduce the communication burden of high-precise clock systems, it is imperative to investigate the clock synchronization control with event-triggered scheme, which is the second motivation.

In general, for the clock systems in industrial WSN, the clock accuracy needs to be sub-microsecond or even microsecond. Hence, it is essential to design an accurate clock synchronization mechanism for high-precise clock systems. In this paper, we attempt to develop an event-triggered synchronization strategy for high-precise clock systems with switching topologies. The contributions of this paper are given as follows:1. A clock model of the clock node is established. With the concept of offset and skew, the model of whole clock systems is illustrated with switching topologies. Besides, an event-triggered strategy is proposed for high-precise clock systems.

2. A synchronization strategy for clock systems with switching network topologies is presented and the sufficient condition for the synchronization of high-precise clock systems with switching topologies is obtained.

3. The clock synchronization problem for clock systems is described as an optimization problem. By solving the optimization problem, the optimal event-triggered weighting matrices and controller gains can be obtained.

2 Problem formulation

In this section, the model of clock systems which consists N unperfected clock nodes and a reference clock node in WSN is first given. Then the communication framework of clock systems with switching topologies and the event-triggered scheme are presented.

2.1 Clock model

In WSN, the local clock information is usually given by a crystal oscillator which is operating with a specific frequency. The reference clock is an ideal clock which the frequency deviation of crystal oscillator is always zero. In fact, the crystal frequency of clock is often affected by the crystal itself and the external environment, which means the clock is a biased clock and has the frequency deviation and phase noise.

For the unperfected clock i, set ci(k) and γi(k) as the clock value and clock rate, respectively. For a free clock, the clock value of clock node i can be represented as(1) ci(k+1)=ci(k)+γi(k)h+ωci(k)

where h is the sample interval and ωci(k) is the phase noise.

Generally, the clock rate often exists a certain amount of randomness due to the changes of temperature, power supply, and mechanical vibration, etc. The dynamic of clock rate can be described as(2) γi(k+1)=γi(k)+ωγi(k)

where ωγi(k) is the clock rate noise which is depended on the disturbance fi(k) and noise εi(k). Therefore,(3) ωγi(k)=fi(k)+εi(k).

Indeed, fi(k) is a periodic signal and εi(k) can be described as a Gaussian process. Then define the clock state vector xi(k)=[ci(k),γi(k)]T and the clock disturbance signal ωi(k)=[ωci(k),ωγi(k)]T. Hence, with (1) and (2), the state model of a free clock is given as(4) xi(k+1)=Axi(k)+ωi(k)

where A=[1h01].

However, the equation (4) describes the free clock, which means the clock is updated according to its own deviation frequency and the deviation from the accurate reference clock is usually increasing. Therefore, to achieve the clock synchronization, it is necessary to design a controller to regulate the unperfected clock, so as to maintain the unperfected clock within a pre-defined synchronization error range and the clock synchronization of clock systems in WSN can be achieved.

Then, we add the control input to a clock node. The state space model of a clock with control input ui(k) is given as(5) xi(k+1)=Axi(k)+Bui(k)+ωi(k)

where B=[1001].

In addition, the reference clock can be reformulated as(6) x0(k+1)=Ax0(k)

where x0(k)=[c0(k),γ0(k)]T. For the reference clock, we assume it is not affected by the phase noise and clock rate noise. In addition, the reference clock has a standard clock rate.

2.2 Communication framework of clock systems

In this subsection, we utilize the graph theory and Markov chain to describe the relationship among the clock nodes in WSN. First, we introduce the graph theory to describe the information relation of clock nodes in WSN.

The connection of N unperfected clock nodes is depicted by a graph G(X,ε,Λ), where X={x1,x2,...,xN}. ε⊆X×X is the communication edge set of unperfected clock nodes. Λ=[aij] is the adjacency matrix which can describe the communication edges of clock nodes and aii=0. (xi,xj) is the edge of clock node xi to clock node xj. If (xi,xj)∈ε, the clock node xj is the neighboring clock node of xi, aij=1. If not, aij=0. Set Δ as the diagonal in-degree matrix. The in-degree of clock node xi is ∑j=1Naij, then the Laplace matrix of G is L=Δ−Λ. In addition, G˜ presents the connection of N unperfected clock nodes and the reference clock node, and define Θ=diag{θ1,θ2,...,θN}∈RN×N. If the reference clock node is a neighbor of clock node xi, θi=1; otherwise, θi=0. If there exists a path in G˜ from every clock node xi to reference clock node, then the reference clock node is globally reachable in G˜ [28], [29]. We assume the reference clock node is globally reachable in this paper. For the time-varying communication topologies, the Markov chain is introduced to describe the topologies.

Define a switching signal χk (k∈N+) and χk∈S={1,2,...,q} is a Markov chain. The communication graph of clock node systems keeps switching within G˜(χk)∈{G˜(1),G˜(2),...,G˜(q)}. prob{χk+1=η|χk=β}=πβη is the switching probability and prob{χk=β}=πβ(k). πβη is the single step transition probability from mode β to η and ∑η=1qπβη=1. πβ(k) is the transition probability of G˜(β) with initial probability prob{χ0=β}=π0β. Define Π(k)=[π1(k),π2(k),...,πq(k)]T to describe the probability distribution. Besides, Π0(k)=[π01(k),π02(k),...,π0q(k)]T is the initial probability distribution. The transition probability matrix is π=[πβη]q⁎q and Π(k+1)=πTΠ(k) [30].

2.3 Event-triggered strategy and control objectives

Then we design the event-triggered scheme. For the unperfected clock node i, the state change of i-th clock node from the last event to time instant k is(7) ei(k)=xi(k)−xi(kmii),

where kmii is the mi-th triggered instant for clock node i. The event-triggered condition for clock node i is(8) eiT(k)Ω(χk)ei(k)≥δi(χk)viT(k)Ω(χk)vi(k)

where Ω(χk)>0 is the weighting matrix and δi(χk)(i=1,⋯,N)>0 is the threshold parameter. In addition, vi(k)=∑j=1Naij(χk)(xi(kmii)−xj(kmjj))+θi(χk)(xi(kmii)−x0(k)), where mj=arg⁡minϵ⁡{k−kϵj|k≥kϵj,ϵ∈N+}. Setting ϕi(k)=eiT(k)Ω(χk)ei(k)−δi(χk)viT(k)Ω(χk)vi(k) and the next triggered instant kmi+1i for clock node i is(9) kmi+1i=kmii+min⁡{li|ϕi(kmii+li)≥0,li∈N+}

where, li represents the event-triggered time interval.

Remark 1 The above event-triggered scheme decides whether the clock value and clock rate are transmitted to the local controller and its neighboring clock nodes. The condition (8) means the clock value and clock rate of a clock node are not transmitted to its neighboring clock nodes if the clock change is in the allowable range, which can reduce the packet transmission and controller updating. In addition, for the discrete clock systems, one has kmi+1i−kmii≥h, which means the Zeno-behavior is not occurred.

Then we define the clock offset Δci(k) as the difference of the unperfected clock value ci(k) and the reference clock value c0(k). It means(10) Δci(k)=ci(k)−c0(k).

Similarly, set the clock skew Δγi(k) as the difference of the unperfected clock rate γi(k) and the reference clock rate γ0(k). It yields(11) Δγi(k)=γi(k)−γ0(k).

The clock synchronization strategy needs to adjust the clock offset and clock skew of each unperfected clock node converged to zero. In addition, the effect of the phase noise ωci(k) and the rate noise ωγi(k) should be reduced. Set x˜i(k)=[Δci(k),Δci(k)]T=xi(k)−x0(k), the above description can be represented as limk→∞⁡‖x˜i(k)‖=0.

Hence, the objectives of clock synchronization for high-precise clock systems with switching topologies can be given as follows:

(1) For the convergence of clock offset and clock skew, design an event-triggered controller for each unperfected clock node which achieves limk→∞⁡E‖x˜i(k)‖=0.

(2) To reduce the effect of the phase noise and rate noise, the clock systems should meet the H∞ performance.

(3) For the optimization of clock offset, clock skew, and control input, investigate a related objective function and optimize the function.

For above objective (3), the objective function is represented as:(12) J=∑k=0∞E{∑i=1N{x˜iT(k)Qx˜i(k)+uiT(k)Rui(k)}}

where, Q,R∈R2×2 are set as positive matrices.

With switching topologies, the event-triggered controller for clock i is designed as(13) ui(k)=K(χk)∑j=1Naij(χk)[xi(kmii)−xj(kmjj)]+K(χk)θi(χk)[xi(kmii)−x0(k)]

where, K(χk) is the controller gain for switching topologies. In addition, aij(χk) and θi(χk) are also varying with different topologies.

With the unperfected clock model (5), clock state change (7), and controller (13), the clock state of clock node i is represented as(14) xi(k+1)=Axi(k)+BK(χk)∑j=1Naij(χk)[xi(k)−xj(k)]+BK(χk)θi(χk)[xi(k)−x0(k)]−BK(χk)∑j=1Naij(χk)[ei(k)−ej(k)]−BK(χk)θi(χk)ei(k)+ωi(k).

Then, for the description of whole high-precise clock systems with a reference clock node and N unperfected clock nodes, set X˜(k)=[x˜1T(k),x˜2T(k),...,x˜NT(k)]T, E˜(k)=[e1T(k),e2T(k),...,eNT(k)]T, W˜(k)=[ω1T(k),ω2T(k),...,ωNT(k)]T. As a result, the high-precise clock systems can be given as(15) X˜(k+1)=[IN⊗A+H(χk)⊗BK(χk)]X˜(k)−H(χk)⊗BK(χk)E˜(k)+W˜(k)

where H(χk)=L(χk)+Θ(χk), ⊗ is the Kronecker product, and IN is the N-dimensional identity matrix.

For the objective function (12), it is converted as(16) J=∑k=0∞E{X˜T(k)(IN⊗Q)X˜(k)+[X˜(k)−E˜(k)]T[HT(χk)H(χk)⊗KT(χk)RK(χk)]×[X˜(k)−E˜(k)]}.

Hence, the clock synchronization for high-precise clock systems is transformed as the stability problem of (15). Then, the stability of clock systems (15) and the optimization of (16) will be analyzed.

3 Main results

The sufficient condition for the stable of clock systems (15) is first analyzed in this section. Then, the H∞ performance for phase noise and rate noise is provided. Afterwards, the optimization problem for obtaining event-triggered weighting matrices and controller gains is solved.

Theorem 1 With the given parameter matrixδ=diag{δ1(χk),δ2(χk),...,δN(χk)}and under the event-triggered condition(8), the clock systems(15)are asymptotically stable when there are no phase noise and rate noise, if there existsP(χk)>0and the following condition holds(17) [Π1−P(χk)+S˜+Q˜+R˜⁎Π2−R˜−S˜Π3+R˜+S˜]<0

whereΠ1=[A˜+H˜(χk)]TP′[A˜+H˜(χk)],Π2=−H˜T(χk)P′[A˜+H˜(χk)],Π3=H˜T(χk)P′H˜(χk)−IN⊗Ω(χk),A˜=IN⊗A,H˜(χk)=H(χk)⊗BK(χk),S˜=HT(χk)δH(χk)⊗Ω(χk),Q˜=IN⊗Q,R˜=HT(χk)H(χk)⊗KT(χk)RK(χk),P′=∑χk+1=1qπχkχk+1P(χk+1). In addition, ⁎ is the symmetric element.

Proof For the clock systems (15), a stochastic Lyapunov function is designed as(18) V(k)=X˜T(k)P(χk)X˜(k).

With the clock systems (15), the difference of (18) is calculated as(19) ΔV(k)=E[V(k+1)]−V(k)=X˜T(k+1)E[P(χk+1)]X˜(k+1)−X˜T(k)P(χk)X˜(k)=X˜T(k)Π1X˜(k)+E˜T(k)H˜T(χk)P′H˜(χk)E˜(k)+2E˜T(k)Π2X˜(k)−X˜T(k)P(χk)X˜(k).

For clock node i, when kmi≤k<km+1i and with inequation (8), one can see that(20) ∑i=1Nϕi(k)=∑i=1N[eiT(k)Ω(χk)ei(k)−δi(χk)viT(k)Ω(χk)vi(k)]<0.

For the whole clock systems, it has(21) [X˜(k)−E˜(k)]TS˜[X˜(k)−E˜(k)]−E˜T(k)(IN⊗Ω(χk))E˜(k)>0.

Then with (19) and (21), if (17) is satisfied, we can have(22) ΔV(k)<X˜T(k)Π1X˜(k)+E˜T(k)Π3E˜(k)++2E˜T(k)Π2X˜(k)+[X˜(k)−E˜(k)]TS˜×[X˜(k)−E˜(k)]−X˜T(k)P(χk)X˜(k)<−{X˜T(k)Q˜X˜(k)+[X˜(k)−E˜(k)]TR˜[X˜(k)−E˜(k)]}.

By defining Ψ(k)=[X˜T(k),E˜T(k)]T and with (22), one can obtain(23) ΔV(k)<ΨT(k)[Π1−P(χk)+S˜+Q˜+R˜⁎Π2−R˜−S˜Π3+R˜+S˜]Ψ(k).

If (17) in Theorem 1 is satisfied, it means ΔV(k)<0 and we have(24) limk→∞⁡E[V(k)]=0.

Therefore, we achieve(25) limk→∞⁡E[‖x˜i(k)‖]=0.

With equation (25), the clock offset and clock skew of each unperfected node can converge to zero. Besides, the clock systems (15) are asymptotic stable. The clock synchronization for high-precise clock systems is achieved. Next, considering the nonzero phase noise and rate noise, the analyzation of H∞ performance for the effect of phase noise and rate noise is given in Theorem 2. □

Theorem 2 With the given parameter matrix δ=diag{δ1(χk),δ2(χk),...,δN(χk)} and under the event-triggered condition (8) , the clock systems (15) are stable and meet H∞ performance with positive parameter η, if there exists P(χk)>0 and the following condition holds (26) [Π4⁎⁎Π2−R˜−S˜Π3+R˜+S˜⁎P′[A˜+H˜(χk)]−P′H˜(χk)−η2I2N+P′]<0

where Π4=Π1−P(χk)+S˜+Q˜+R˜+I2N .

In addition, the upper bound of (16) is (27) sup⁡J=X˜T(0)P(χ0)X˜(0).

Proof Set Φ(k)=[ΨT(k),W˜T(k)]T. For the nonzero phase noise and rate noise under zero-initial condition, we can conclude that(28) ΔV(k)+X˜T(k)X˜(k)−η2W˜T(k)W˜(k)<ΦT(k)[Π4⁎⁎Π2−R˜−S˜Π3+R˜+S˜⁎P′[A˜+H˜(χk)]−P′H˜(χk)−η2I2N+P′]Φ(k).

If (26) in Theorem 2 is satisfied, it has(29) ΔV(k)+X˜T(k)X˜(k)−η2W˜T(k)W˜(k)<0.

For k from zero to infinite, we have(30) ∑k=0∞{ΔV(k)+X˜T(k)X˜(k)−η2W˜T(k)W˜(k)}<0.

With zero-initial condition, one has(31) ∑k=0∞∑i=1N[x˜iT(k)x˜i(k)−η2ωiT(k)ωi(k)]<0.

Hence, the clock systems (15) meet H∞ performance, which means the effect of the phase noise and rate noise can be reduced.

Then on the basis of defined condition(32) ΔV(k)<−{X˜T(k)Q˜X˜(k)+[X˜(k)−E˜(k)]TR˜[X˜(k)−E˜(k)]},

and by accumulating (32) from zero to infinite, one has(33) J=E[V(0)]=E[X˜T(0)P(χ0)X˜(0)].

Therefore, the upper bound of objective function can be achieved as (27).

For obtaining event-triggered weighting matrices and controller gains, we give Theorem 3 to solve the nonlinear terms of (26) in Theorem 2. □

Theorem 3 With the given parameter matrix δ=diag{δ1(χk),δ2(χk),...,δN(χk)} and under the event-triggered condition (8) , the event-triggered weighting matrices and controller gains are solvable, if there exist P(χk)>0 , Y(χk)>0 and the following condition holds (34) [Π5⁎⁎⁎⁎−S˜−IN⊗Ω(χk)+S˜⁎⁎⁎00−η2I2N⁎⁎K˜(χk)−K˜(χk)0−R¯−1⁎πχk⊗Π6−πχk⊗Π7πχk⊗I2N0−Y˜]<0

where Π5=−P(χk)+S˜+Q˜+I2N , Π6=A˜+H¯(χk)K¯(χk) , Π7=H¯(χk)K¯(χk) , H¯(χk)=H(χk)⊗B , K¯(χk)=IN⊗K(χk) , πχk=[πχk10.5,πχk20.5,...,πχkq0.5]T , Y˜=diag{Y(1),Y(2),...,Y(q)} , Y(χk)=P−1(χk) , and R¯=HT(χk)H(χk)⊗R .

Proof The inequation (26) is converted as(35) [Π5⁎⁎−S˜−IN⊗Ω(χk)+S˜⁎00−η2I2N]+Π8TR¯Π8+Π9TP′Π9<0,

where, Π8=[K¯(χk),−K¯(χk),0], Π9=[A+H¯(χk)K¯(χk),−H¯(χk)K¯(χk),I2N]

Through inequation (35) and utilizing the Schur complement [31], the Theorem 3 can be obtained.

Then we optimize the objective function. First, set X˜T(0)P(χ0)X˜(0)≤Γ, the minimization of (27) can be converted into(36) min⁡Γs.t.X˜T(0)P(χ0)X˜(0)≤Γ.

The constraint condition in optimization problem (36) can be represented as(37) [Γ⁎X˜(0)Y(χk)]≥0.

For the constraints Y(χk)=P−1(χk), it can be converted as the rank constrained linear matrix inequalities as follows [32](38) [P(χk)⁎IY(χk)]≥0,rank[P(χk)⁎IY(χk)]≤2N.

As a result, the clock synchronization strategy for clock systems in WSN can be described as the follow optimization problem (39).(39) min⁡Γs.t.(15),(34),(37),and(38).

 □

Remark 2 By solving the optimization problem (39), the event-triggered weighting matrices and controller gains can be obtained as well as the optimization of the objective function. In addition, the solution of (39) can achieve the convergence of clock offset and clock skew, and reduce the effect of phase noise and rate noise. It means all control objectives are achieved.

4 Numerical example

In this section, we conduct numerical experiments to validate the proposed event-triggered clock synchronization strategy for high-precise clock systems. In the example, we give the clock systems which contains four clock nodes with a reference node and three unperfected clock nodes.

We set that the communication topologies of clock systems switch from three possible topologies which are shown in Fig. 1 and define as G˜(1), G˜(2), G˜(3). With Fig. 1, the clock 0 is the reference clock node, and others are unperfected nodes which need to be synchronized.Figure 1 Possible topologies of clock systems.

Figure 1

The switching topologies are driven by a Markov chain and the transition probability matrix is π=[0.50.30.20.30.60.10.30.30.4]. In addition, G˜(1) is the initial topology.

For the entire clock systems, the initial clock offsets and skew values of nodes 1, 2, and 3 are given in Table 1. The phase noise ωci(k) and the clock rate noise ωγi(k) are assumed as Gussian noise with zero mean value and the standard deviation is 10−6. The event-triggered parameters are designed as δi(1)=0.055, δi(2)=0.045, and δi(3)=0.095, (i=1,2,3) for G˜(1), G˜(2), G˜(3), respectively. The weighting matrices of (12) is set as Q=10I2 and R=2I2.Table 1 Initial clock offset and skew values.

Table 1node	value	
Offset of node 1	8.3s	
Offset of node 2	5.2s	
Offset of node 3	6.6s	
Skew of node 1	0.1	
Skew of node 2	0.2	
Skew of node 3	0.15	

The simulation time is set as 30 seconds. In Fig. 2, topologies G˜(1), G˜(2), and G˜(3) are shown as modes 1, 2 and 3, respectively. It can be seen the Markov switching sequences clearly. By solving the optimization problem (39), we can obtain the controller gains K(1)=[−0.0579−0.00580−0.058], K(2)=[−0.0816−0.0080.0001−0.0817], and K(3)=[−0.0866−0.00850.002−0.0868]. In addition, the event-triggered weighting matrices Ω(1)=[9.10920.49160.49169.4418], Ω(2)=[14.16490.74620.746214.6778], and Ω(3)=[10.25420.53250.532510.6245].Figure 2 Markov switching sequences.

Figure 2

In the example, the clock times of clock systems are shown in Fig. 3. From Fig. 3, one can see that the clock times of unperfected clock nodes can be synchronized with the reference clock. The Fig. 4 and Fig. 5 give the offsets and skews of clock systems. The offsets and skews of unperfected clock nodes can be converged. In Fig. 6, a small segment of the clock offsets at the steady synchronization state is intercepted. From Fig. 6, we can find that the synchronization accuracy reaches microsecond level. It means the proposed method in this paper can achieve clock synchronization for high-precise clock systems.Figure 3 Clock times of clock systems.

Figure 3

Figure 4 Offsets of clock systems.

Figure 4

Figure 5 Skews of clock systems.

Figure 5

Figure 6 Clock offsets at the steady synchronization state.

Figure 6

The triggered instants and intervals of unperfected clocks are shown in Fig. 7. In Fig. 7, we give the triggered instants and intervals for first 10 seconds. With the unperfected clock nodes, the number of triggered instants is 38, 31, and 49 for unperfected clock nodes 1, 2, and 3, respectively. Comparing with the number of samples, the number of transmitted data is significantly reduced for each unperfected clock node.Figure 7 Transmission instants and intervals of unperfected clocks.

Figure 7

Then, the comparation results with sample-data strategy are shown in Fig. 8 and Fig. 9. The Fig. 8 and Fig. 9 show the offsets and skews of clock nodes under the sample-data strategy. For the proposed clock synchronization strategy and the sample-data strategy, the only difference is the sample-data strategy needs all sampling information. With Fig. 4, Fig. 5, Fig. 8, and Fig. 9, both two strategies can achieve clock synchronization. The proposed clock synchronization strategy can have the almost same performance with less clock data.Figure 8 Offsets of clock systems with sample-data strategy.

Figure 8

Figure 9 Skews of clock systems with sample-data strategy.

Figure 9

Afterwards, we give a comparation with the method in reference [27]. With the same initial condition, the simulation results of reference [27] are shown in Figure 10, Figure 11. Although the results in reference [27] can achieve the clock synchronization, the synchronization speed is slower than the proposed clock synchronization strategy. Obviously, the proposed strategy is more suitable for clock synchronization of high-precise clock systems with switching topologies.Figure 10 Offsets of clock systems with reference [27].

Figure 10

Figure 11 Skews of clock systems with reference [27].

Figure 11

5 Conclusion

In this paper, an accurate event-triggered clock synchronization mechanism for high-precise clock systems with switching topologies is presented. The event-triggered synchronization method can make the communication and computation more efficient, and reduce the number of packet exchanges. According to the proposed clock synchronization scheme, the offsets and skews of clocks systems can converge to zero which means the high-precise clock synchronization can be achieved. In addition, the effect of phase noise and rate noise can be reduced. However, the communication delay in high-precise clock systems is an essential factor which need to be fully considered and it is different from the general multi-agent systems. In the future work, we will consider the communication delay of the high-precise clock systems.

CRediT authorship contribution statement

Hui Zhao: Writing – review & editing, Writing – original draft, Software, Methodology. Xuewu Dai: Writing – review & editing, Conceptualization. Yuan Zhao: Writing – review & editing, Writing – original draft.

Declaration of Competing Interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Data availability statement

The authors confirm that the data supporting the findings of this study are available within the article.

Acknowledgements

This work was supported in part by the 10.13039/501100001809 National Natural Science Foundation of China under Grant 62303329 , in part by the Natural Science Foundation of Liaoning under grant 2023-BASA-236 , in part by the Education Department Foundation of Liaoning under grant LJKQZ20222328 .
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