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Sci Rep
Sci Rep
Scientific Reports
2045-2322
Nature Publishing Group UK London

39237808
71612
10.1038/s41598-024-71612-y
Article
A new positive output DC–DC buck–boost converter based on modified boost and ZETA converters
Hosseinpour Majid hoseinpour.majid@uma.ac.ir

1
Heydarvand Milad 1
Azizkandi Mahmoodreza Eskandarpour 2
1 https://ror.org/045zrcm98 grid.413026.2 0000 0004 1762 5445 Department of Electrical Engineering, University of Mohaghegh Ardabili, Ardabil, Iran
2 https://ror.org/04b6b6f76 grid.462661.1 0000 0004 0542 7070 Department of Electrical and Computer Engineering, NC State University, Raleigh, NC USA
5 9 2024
5 9 2024
2024
14 2067512 5 2024
29 8 2024
© The Author(s) 2024
2024
https://creativecommons.org/licenses/by-nc-nd/4.0/ Open Access This article is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License, which permits any non-commercial use, sharing, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if you modified the licensed material. You do not have permission under this licence to share adapted material derived from this article or parts of it. The images or other third party material in this article are included in the article’s Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by-nc-nd/4.0/.
A new DC–DC buck–boost converter with a wide conversion ratio is presented in this paper. The proposed buck–boost converter consists of a combination of modified boost converter and ZETA converter, which has the advantages of both converters such as continuous input/output current and positive polarity of the output voltage. The combination of these two converters achieves semi-quadratic voltage gain and makes the proposed converter suitable for industrial and renewable energy applications. With a voltage gain higher than that of the ZETA converter and modified boost converter, the proposed converter also reduces input current stress due to its continuity. Two operating states are available for this converter in continuous conduction mode. This converter has two switches that operate simultaneously and can be easily controlled. The converter's output voltage ripple and output capacitor current stress are reduced as a result of continuous output current. Computational analysis and the introduced structure efficiency considering the influence of parasitic elements are presented in this paper. The small signal modelling and closed-loop control, as well as simulation and experimental results are also presented. This converter has also been compared with other similar and recently presented topologies. Finally, a 40–60 W, 20–76 V for boost mode and 10 V for buck mode prototype was implemented to verify the accuracy of the computational analysis.

Keywords

Buck–boost converter
ZETA converter
Non-inverting
Voltage gain
Voltage and current stress
Subject terms

Renewable energy
Electrical and electronic engineering
issue-copyright-statement© Springer Nature Limited 2024
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pmcIntroduction

Climate change, global warming, and pollution from fossil fuels have made renewable energy sources like fuel cells, solar panels, and wind energy more appealing over recent decades 1. Renewable energies are environmentally-friendly and have become competitive due to the increasing development of power electronics and can meet load demand using power electronic converters, especially DC–DC converters 2. Many applications use DC–DC converters such as grid connections, light emitting diodes (LED), battery power systems, uninterrupted power supplies (UPS), and household appliances 3.

DC–DC converters are the main pillars of renewable energy equipment and are used to adjust their voltage and deliver to the DC-AC inverter and the grid 4. These converters can be classified into isolated and non-isolated categories 5. Despite the high voltage gain and low voltage stress on the switches, isolated converters have disadvantages such as high voltage spikes due to the transformer leakage inductance, large circuit volume and high manufacturing costs 6. Several solutions exist to solve the spike problem, such as active or passive clamps. However, they complicate the circuit, as well as the way it is controlled 7. In contrast, non-isolated converters are more commonly used because of their simple structure, small circuit volume, and low manufacturing costs 8. The buck–boost converter is one of the non-isolated converters that can operate in a wide voltage conversion range and increase and decrease the input voltage 9. SEPIC, ZETA, and CUK converters are conventional buck–boost converters 10. Even though these converters have the advantages mentioned above, they also have drawbacks, such as discontinuous input current (conventional buck–boost and ZETA converters), negative output voltage polarity (conventional buck–boost and CUK converters), elevated voltage levels on switches, and reduced operational efficacy that limit their applications 11.

In order to surmount the limitations of traditional converters, various improved buck–boost structures have been proposed in recent years. References 12–15 present buck–boost converters with continuous input current and positive output voltage polarity, which are suitable for industrial applications and renewable energies, but do not provide continuous output current. Reference 12 presents a semi-quadratic converter with a high voltage gain. Despite this, the control method of this converter is complex, and it has a large number of elements. Based on an active switched network, the converter presented in 13 has high voltage gain and low voltage stress on the switches and the diode. A single-switch buck–boost converter based on the SEPIC converter is presented in 14, which is easy to control due to its single-switch. Even though this converter has a large number of elements, the voltage gain is low. In reference 15, a converter based on SEPIC is presented, which the voltage stress of its switches is low.

The converters presented in 16–18 have continuous input and output currents and positive output voltage polarity. A converter with a quadratic voltage conversion ratio which is presented in 16 has a small number of elements, but a low voltage gain, and a relatively high voltage stress on the switches. The voltage strain experienced by the switch and diodes in the converter outlined in reference 18 exceeds that of the output voltage. In reference 19, an additional buck–boost converter exhibiting a broad conversion ratio and continuous input current is presented, suitable for industrial and renewable energy applications. However, the output voltage polarity of this converter is negative, and the output current exhibits intermittent behavior. In 20 and 21, buck–boost converters are presented with continuous output current and positive output voltage polarity. However, their input current is discontinuous. The converter presented in 20 is a single-switch buck–boost converter based on the ZETA converter, and its voltage conversion ratio is twice that of the ZETA converter. However, output voltage changes are not wide. In 21, another quadratic buck–boost converter is presented, which covers a wide range of conversion ratio.

A continuous input and output current converter is presented in 22 with a wide range of voltage conversion. However, the output voltage polarity of this converter is negative. The converters presented in 23 and 24 have positive output voltage polarity. Nevertheless, their input and output currents are discontinuous. The converter presented in 23 is a buck–boost converter using a quasi-Z impedance network, which has a higher conversion ratio and a lower duty cycle than the conventional buck–boost converter, which leads to increased efficiency. However, owing to the elevated gradient of the voltage gain curve, it is difficult to adjust the converter's voltage and control. In 24, a quadratic buck–boost converter is designed with fewer elements and consists of a pair of L-C networks and two switches that turn ON/OFF simultaneously. In reference 25, a buck–boost converter with discontinuous input/output current and negative output voltage polarity is presented. This converter is a semi-quadratic converter with a wide conversion ratio that uses a voltage multiplier cell (VMC) on the input side to increase the output voltage.

To overcome the aforementioned disadvantages of buck–boost converters, this paper presents a semi-quadratic buck–boost converter based on modified boost converter and ZETA converter, which has advantages such as continuous input and output currents and positive polarity of output voltage. Due to its semi-quadratic voltage gain, the introduced structure has a wide range of conversion ratio, and its simultaneous operation of the power switches makes its control easy. Also, the proposed converter has high efficiency and due to the importance of efficiency in its operation, the operation cost is also reduced and it is economical in terms of cost–benefit.

The rest of the paper is organized as follows. The structure of the proposed converter and the operation modes, CCM and DCM (Discontinuous Conduction Mode), are presented in section "Proposed converter and steady state analysis". Section "Proposed converter and steady state analysis" also describes the design parameters, as well as calculations of real voltage gain and efficiency considering the influence of parasitic parameters for converter performance. The comparison between the proposed converter and other similar converters is presented in section "Comparison of the proposed converter with similar converter", the small signal modeling of the proposed converter is presented in section "Small signal modeling of the proposed converter", the simulation and experimental results to verify the computational analysis are presented in section "Simulation and experimental results", and finally, the conclusion is presented in section "Conclusion".

Proposed converter and steady state analysis

The proposed buck–boost converter is shown in Fig. 1. This converter includes two switches (S1, S2), three diodes (D1, D2, D3), three inductors (L1, L2, L3), four capacitors (C1, C2, C3, Co) and a load (Ro) to achieve the high voltage gain. The switches of this converter are turned ON/OFF simultaneously. As seen in Fig. 1, this converter does not have common ground feature. Therefore, instead of being used in photovoltaics, this structure is used in cases such as switched-mode power supplies, batteries, portable electronic devices, and electric vehicles.Fig. 1 The proposed buck–boost converter.

Due to the presence of inductors L1 and L3 at the input and output ports of the proposed converter, the input and output current are continuous. The operational states of the converter in continuous conduction mode (CCM) are depicted in Fig. 2. The subsequent assumptions have been applied for simplifying the steady-state analysis.The circuit Semiconductor elements such as switches and diodes are ideal.

The capacitors possess ample capacitance to maintain a constant voltage.

The input inductor is regarded as sufficiently large, resulting in the neglect of its current ripple.

Fig. 2 Operation modes of the suggested converter: (a) state 1; (b) state 2.

The introduced topology key waveforms, which have the power switches gate pulses (VGS1, GS2), the inductors current (iL1, iL2, iL3) and the capacitors current (iC1, iC2, iC3, iCo), are shown in Fig. 3. The operating states are also described below.Fig. 3 Introduced converter key waveforms.

State1 [t0, t1]: During this mode, the power switches S1 and S2 are ON, and the diodes D1, D2, and D3 are reverse biased. It can be seen from Fig. 2a that inductor L1 is charged by the input source, and inductor L2 is charged by capacitors C1 and C2. Additionally, the capacitors C1, C2, C3, and Co discharge within the inductor L3 and the load Ro. The voltage across the inductors and the current through the capacitors are provided in Eqs. (1) and (2).1 vL1=L1diL1dt=VivL2=L2diL2dt=vC1+vC2vL3=L3diL3dt=vC1+vC2+vC3-Vo

2 iC1=C1dvC1dt=-iL2-iL3iC2=C2dvC2dt=-iL2-iL3iC3=C3dvC3dt=-iL3iCo=CodvCodt=iL3-io

State2 [t1, t2]: As a result of this time interval, both main switches are OFF, and D1, D2 and D3 are forward-biased. According to Fig. 2b, the capacitors C1 and C2 are charged by both the input source and the inductor L1 through diodes D1 and D2, respectively. The energy accumulated in the inductor L2 charges the capacitor C3 through the diode D3. Meanwhile, the inductor L3 provides energy to both the capacitor Co and the output load Ro. Furthermore, C1 and C2 have the same voltage. The voltage of the inductors and the current of the capacitors in this case are as follows.3 vL1=L1diL1dt=Vi-vC1vL2=L2diL2dt=-vC3vL3=L3diL3dt=-VovC1=vC2

4 iC1=C1dvC1dt=iL12iC2=C2dvC2dt=iL12iC3=C3dvC3dt=iL2iCo=CodvCodt=iL3-io

Ideal voltage gain

In this section, to determine the steady-state voltage gain, the volt-second balance principle is used for inductors L1, L2 and L3 in a switching period. According to the volt-second balance, the average inductor voltage in a switching period under steady-state conditions should be zero.

By applying the volt-second balance principle on the inductors L1, L2 and L3 in a switching period, the following results are obtained:5 L1:DVi+(1-D)(Vi-vC1)=0

6 L2:D(vC1+vC2)+(1-D)(-vC3)=0

7 L3:D(vC1+vC2+vC3-Vo)+(1-D)(-Vo)=0

By using the Eqs. (3) and (5), the voltage of capacitors C1 and C2 can be obtained as follows:8 vC1=vC2=Vi1-D

In addition, the voltage of capacitor C3 can be calculated using the relations (6) and (8) as follows:9 vC3=2DVi(1-D)2

By using the Eqs. (6) and (7), it is obtained:10 vC3=Vo

From (9) and (10), the output voltage is obtained as follows:11 Vo=2DVi(1-D)2

As a result, the voltage conversion ratio of the proposed converter is calculated as follows:12 Mideal=VoVi=2D(1-D)2

The proposed converter functions in the boost mode when D exceeds 0.268, while it operates in the buck mode for D values less than 0.268. The border between the buck and boost modes is shown in Fig. 4.Fig. 4 The border between the buck and boost modes.

DCM operation mode

Discontinuous Conduction Mode (DCM) has three modes. Modes 1 and 2 of DCM are similar to those of CCM. During the third mode, all switches and diodes are deactivated. Consequently, the voltage across the inductors is rendered to zero. The equivalent circuit representing the third mode of the DCM is illustrated in Fig. 5a. Furthermore, the waveforms depicting DCM operation modes are displayed in Fig. 5b. The mean current across the inductors equates to the mean current flowing through the diodes and the average output current.Fig. 5 DCM operation mode: (a) equivalent circuit of the third mode of DCM; (b) operation waveforms for DCM.

In the Continuous Conduction Mode (CCM), the average current of the inductors must surpass half of the current ripple across the inductors (IL > 1/2∆iL). To achieve a standard inductor, the time constant τL1,2,3 is defined as τL1,2,3 = L1,2,3f./R. Accordingly, inductors L1, L2 and L3 have the boundary conditions presented in Eq. (13).13 τL1B=(1-D)48DτL2B=(1-D)22DτL3B=1-D2τLtotalB=(1-D)4+4(1-D)2+4D(1-D)8D

According to Eq. (13), the correlation between the time constant τL being greater than τLB and the duty cycle D is depicted in Fig. 6 (τL > τLB). This implies that if τL surpasses τLB, the circuit operates in CCM; otherwise, it operates in DCM.Fig. 6 Boundary conditions for the proposed converter.

Parameters design

Inductors design

During the on-state of the switches S1 and S2, the inductors' current increases linearly. It is assumed that the ripples in the inductor current of the proposed converter are equal to 40% of its average current. Equation (1) indicates that inductors L1, L2 and L3 are in the following ranges based on the voltage relation of capacitors.14 L1≥5(1-D)4Vo8DfsIoL2≥5(1-D)2Vo2DfsIoL3≥5(1-D)Vo2fsIo

Inductors design

It is necessary to calculate the average current of the capacitors before designing the amount of capacitors. By applying the ampere-second balance principle on the C1, C2, C3 and Co capacitors and applying relations (2) and (4), the inductors average current is obtained as follows.15 IL1=2DIo(1-D)2IL2=DIo1-DIL3=Io

By considering the permissible voltage ripple of 1% and combining Eq. (4) with the average current relations of the inductors, the range of the capacitors can be determined as follows. {#R11}16 C1=C2≥2D21%(1-D)2RofsC3≥D1%RofsCo≥D1%Rofs

Voltage/current stress of power switches and diodes

According to Fig. 2 and using Eqs. (8) and (9), the formula (17) provides the expression for calculating the voltage stress experienced by the switches and diodes in the suggested converter.17 VS1=1(1-D)ViVS2=1+D(1-D)2ViVD1=VD2=1(1-D)ViVD3=2(1-D)2Vi

Also, the current stress of the switches and diodes according to Fig. 2 and using Eq. (15), is as follows:18 IS1,avg=D(1+D)(1-D)2IoIS2,avg=D(1-D)IoID1,avg=ID2,avg=D(1-D)IoID3,avg=Io

Real voltage gain and efficiency with parasitic parameters

This section analyzes the effect of parasitic parameters on output voltage and efficiency. Figure 7 depicts the circuit diagram of the proposed converter, accounting for the impact of parasitic parameters. The equivalent series resistances (ESR) of the inductors and capacitors are denoted as rL and rC, respectively. The on-state resistance of the switches and the internal resistance of the diodes are rS and rD, respectively, and VD is the forward voltage drop of the diodes.Fig. 7 The proposed buck–boost converter circuit with parasitic parameters.

Real voltage gain

In practical conditions, the operational states of the proposed structure closely mirror its operation modes in CCM, taking into account the impact of parasitic parameters. Parasitic parameters include the on-state resistance of switches (rS) equal to 0.05 Ω, internal resistance of diodes (rD) equal to 0.15 Ω, capacitors and inductors ESR (rC, rL) equal to 0.02 Ω and 0.05 Ω, respectively, and the forward voltage drop (VD) is equal to 0.6 V. The voltage of the inductors in the time interval of DTs is as follows.19 vL1=Vi-rLiL1-rS(iL1+iL2+iL3)

20 vL2=vC1+vC2-rLiL2-rS(iL2+iL3)-rC(iL2+iL3)-rS(iL1+iL2+iL3)-rC(iL2+iL3)

21 vL3=vC1+vC2+vC3-Vo-(rL+rC)iL3-rS(iL2+iL3)-rC(iL2+iL3)-rS(iL1+iL2+iL3)-rC(iL2+iL3)

Similarly, in the (1-D)Ts time interval, the inductors' voltage is obtained as follows.22 vL1=Vi-vC1-VD-rLiL1-(rC+rD)iL1/2

23 vL2=-vC3-VD-(rL+rC)iL2-rD(iL2+iL3)

24 vL3=-Vo-VD-rLiL3-rD(iL2+iL3)

From Eq. (15) and Eqs. (19)–(24), the real voltage gain is obtained as follows:25 Greal=Gideal-1-D2(1-D)2VDVi1+1Ro(M1+M2+M3+M4)

The values of M1, M2, M3 and M4 are also presented as follows:26 M1=2D3+2D(1-D)4rSM2=2D4-6D3+11D2-4D+1(1-D)4rLM3=D3-2D2+3D(1-D)3rCM4=3D2-2D+1(1-D)3rD

The graphs of real voltage gain of the proposed converter versus duty cycle are presented in Fig. 8. As can be seen in Fig. 8, the real voltage gain varies with the rL/Ro ratio. In this case, increasing rL/Ro leads to a decrease in the real voltage gain.Fig. 8 Real voltage gain considering parasitic parameters.

Efficiency

In this section, efficiency calculations are analyzed based on the power losses of the proposed converter. The power losses include the power losses of the switches, diodes, inductors and capacitors. Switch losses are partitioned into two components: switching losses and conduction losses, elucidated as follows:27 PLossSwitch=PConductionSwitch+PSwitchingSwitch

28 PConductionSwitch=RDS-onISwitch,rms2PSwitchingSwitch=12VDS-onISwitch,avg(tr+tf)fs

where RDS-on is the on-state resistance of the switch, ISwitch,rms is the root mean square (RMS) of the current passing through the switch, VDS is the constant voltage of the switch, ISwitch,avg is the average current passing through the switch, (tr,tf) are the rise and fall times of the switches respectively, and fs is the switching frequency. The RMS values of switch currents are calculated as follows:29 IS1,rms=∫0DTs(iL1+iL2+iL3)2dtTs=D(1+D)(1-D)2Io

30 IS2,rms=∫0DTs(iL2+iL3)2dtTs=D(1-D)Io

The converter diode losses can be expressed according to the following equation.31 PLossDiode=rDID,rms2+VDID,avg

Here, rD represents the internal resistance of the diode, ID,rms signifies the RMS value of the current flowing through the diode, VD denotes the forward voltage drop of the diode, and ID,avg represents the average current traversing the diode. The RMS values of diode currents are obtained as follows:32 ID1,rms=ID2,rms=∫DTss(12iL1)2dtTs=D(1-D)3Io

33 ID3,rms=∫DTss(iL2+iL3)2dtTs=11-DIo

The winding resistance rL leads to the copper loss of the inductor, which is calculated as follows:34 PLossInductor=rL1IL1,rms2+rL2IL2,rms2+rL3IL3,rms2

where IL1,rms, IL2,rms and IL3,rms are the RMS values of inductors current which are equal to the average current of inductors.

The parasitic resistance rC results in capacitor losses calculated below.35 PLossCapacitor=rC1IC1,rms2+rC2IC2,rms2+rC3IC3,rms2+rCoICo,rms2

The RMS values of the capacitors are calculated as follows:36 IC1&2,rms=∫0DTs(iL2+iL3)2dt+∫DTss(12iL1)2dtTs=D(1-D)3Io

37 IC3,rms=∫0DTsiL32dt+∫DTssiL22dtTs=D1-DIo

38 ICo,rms=∫0DTs(iL3-io)2dt+∫DTss(iL3-io)2dtTs=0

The total losses can be determined by summing the aforementioned losses as follows.39 PLossTotal=∑(PLossSwitch+PLossDiode+PLossInductor+PLossCapacitor)

Finally, the converter efficiency is formulated in the following equation.40 η=PoPo+PLossTotal×100%

Figure 9 shows the efficiency diagram of the proposed converter versus output power at the specified intervals in boost and buck modes. As can be seen, the boost mode efficiency is approximately 97%. Also, the efficiency in buck mode is more than 92%.Fig. 9 Efficiency of the proposed converter versus output power in boost and buck modes.

Figure 10 illustrates the comparison between the efficiency of the proposed converter and various other converters across different intervals of output power under identical conditions. Evidently, the proposed converter demonstrates superior efficiency compared to other converters at identical power levels. It should be noted that the parasitic parameters used in the drawing of Figs. 9 and 10 include the on-state resistance of switches (rS) equal to 0.05 Ω, internal resistance of diodes (rD) equal to 0.15 Ω, capacitors and inductors ESR (rC, rL) equal to 0.02 Ω and 0.05 Ω, respectively, and the forward voltage drop (VD) is equal to 0.6 V.Fig. 10 Comparing the efficiency of the proposed converter with other converters: (a) boost mode; (b) buck mode.

The pie chart of power loss distribution in boost and buck modes is shown in Fig. 11. The boost mode has a higher input current than the output current, while the buck mode has a lower input current than the output current. So, the efficiency in buck mode is lower than the efficiency in boost mode. As a result, buck mode loss is more than boost mode. Power losses of switches, diodes, capacitors and inductors are obtained by considering Eqs. (27) to (38).Fig. 11 Pie chart of power loss distribution: (a) boost mode; (b) buck mode.

In the boost mode, the output voltage increases compared to the input voltage, and the output current also decreases compared to the input current, in the same proportion. On the opposite point, in the buck mode, the output voltage decreases compared to the input voltage, and the output current also increases compared to the input current, in the same proportion. The placement of diode D3 in the proposed circuit is close to the output load and it should pass more current in the buck mode. Since the diode D3 passes the total current of the inductors L2 and L3 in state 2 of the equivalent circuit of the proposed converter, and according to the results of simulation and experiment, the sum of these two currents in the buck mode is about 2.5 times higher than the sum of these two currents in the boost mode. Therefore, the loss contribution of diode D3 in the buck mode has achieved a significant amount.

Comparison of the proposed converter with similar converter

To assess the capabilities of the proposed converter, a comparative analysis was conducted, considering the number of elements, voltage gain, and voltage/current stress of switches and diodes. Specifically, efforts were made to select converters that closely resemble the proposed converter in terms of the total number of components and switches, ensuring a comprehensive and equitable evaluation. Also, a comparison between the proposed converter and other converters in terms of the common ground connection between the input and output ports has been made in Table 1.Table 1 Comparison between buck–boost converters characteristics.

	Switches	Diodes	Capacitors	Inductors	Number of elements	Voltage stress of switches (VS/Vi)	Voltage stress of diodes (VD/Vi)	Current stress of switches (IS/Io)	Current stress of diodes (ID/Io)	Voltage gain	CG	CIC	
12	2	3	5	4	14	1/(1 − D), 1/(1 − D)2	1/(1 − D), (2 − D)/(1 − D)2, (2 − D)/(1 − D)2	2/(1 − D)2, 2/(1 − D)	2D/(1 − D), 1, 1	2D(2 − D)/(1 − D)2	Yes	Yes	
17	2	2	3	3	10	1/(1 − D), D/(1 − D)2	1/(1 − D), D/(1 − D)2	D2/(1 − D)2, D/(1 − D)	D/(1 − D), 1	D2/(1 − D)2	Yes	Yes	
18	1	5	3	3	12	1/(1 − D)2	1/(1 − D), D/(1 − D)2, 1/(1 − D)2, 1/(1 − D), D/(1 − D)2	(D3 − D2 + D)/(1 − D)2	D2/(1 − D), D3/(1 − D)2, D, D, (1 − D)	D2/(1 − D)2	Yes	Yes	
20	1	2	4	3	10	1/(1 − D)	1/(1 − D), 1/(1 − D)	2/(1 − D)	1/(1 − D), 1/(1 − D)	2D/(1 − D)	Yes	No	
21	2	3	4	3	12	1/(1 − D), D/(1 − D)2	1/(1 − D), 1/(1 − D)2, D/(1 − D)2	(1 + D)/(1 − D)2, (1 + D)/(1 − D)	(1 + D)/(1 − D)2, D/(1 − D), D/(1 − D)	D(1 + D)/(1 − D)2	Yes	No	
22	2	2	3	3	10	1/(1 − D), 1/(1 − D)2	1/(1 − D), 1/(1 − D)2	D/(1 − D)2, D/(1 − D)	D/(1 − D), 1	D/(1 − D)2	Yes	Yes	
24	2	2	2	2	8	1/(1 − D), D/(1 − D)2	1/(1 − D), D/(1 − D)2	D3/(1 − D)4, D2/(1 − D)3	D3/(1 − D)4, D2/(1 − D)3	D2/(1 − D)2	Yes	No	
25	2	4	3	3	12	2/(1 − D), 2/(1 − D)2	1/(1 − D), 1/(1 − D), 2/(1 − D), 2D/(1 − D)2	2D/(1 − D)2, 1/(1 − D)	2D/((1 + D)(1 − D)2), 2D/((1 + D)(1 − D)2), (1 + D)/(1 − D)2, 1/(1 − D)	2D/(1 − D)2	Yes	No	
Proposed	2	3	4	3	12	1/(1 − D), (1 + D)/(1 − D)2	1/(1 − D), 1/(1 − D), 2/(1 − D)2	(D(1 + D))/(1 − D)2, D/(1 − D)	D/(1 − D), D/(1 − D), 1	2D/(1 − D)2	No	Yes	
CG common ground, CIC continuous input current.

Number of elements

The combination and number of elements utilized in structures is listed in Table 1. Despite having an equal number of elements, the proposed converter has a higher voltage gain than converters 18 and 21. Furthermore, despite equality in the number of elements and voltage gain between the proposed converter and the converter 25, the proposed converter has a relatively low voltage/current stress on switches and diodes. In addition, converters 17,20,22,24 have fewer elements than the proposed converter, but they have a lower voltage gain. Also, the number of elements of converter 12 is more than the proposed converter. Therefore, its high voltage gain is logical.

Voltage gain comparison

In addition to Table 1, Fig. 12 graphically represents the voltage gain of the comparative converters as a function of the duty cycle. It is obvious that the proposed converter and the converter 25 show a higher voltage gain than the alternative converters at varying duty cycle values except for the converter 12, as shown in Fig. 12. Considering that the converter 12 has more elements than the proposed converter, so the high voltage gain of the converter 12 is also reasonable compared to the proposed converter. In this figure, the voltage gain of converters 17,18,24 is the same. Even though the converters 18 and 21 have the same number of elements, their voltage gain is lower than the suggested topology. As mentioned earlier, despite having the same voltage gain as the proposed converter, the converter 25 has a relatively high voltage/current stress on switches and diodes compared to the proposed converter.Fig. 12 Comparison of voltage gain of the converters versus duty cycle.

Voltage stress comparison of semiconductor devices

Figure 13 shows the relationship between voltage stress of the switches and duty cycle. The voltage stress experienced by switch S1 in the proposed converter corresponds to the voltage stress encountered by switch S1 in converters 12,17,21,22,24 and switch S in converter 20. Furthermore, the voltage stress of the switch S2 in converters 17,21,24 are equivalent, While the voltage stress of the switch S2 in converters 12 and 22 and the voltage stress of the switch S in the converter 18 are the same. As can be seen in Fig. 12, the switch S1 of the proposed converter has a low voltage stress, and even though the switch S2 of the proposed converter has a high voltage stress, it can be ignored due to the high voltage gain of the proposed converter except the converter 12. Also, despite its voltage gain being equal to the proposed converter, the converter 25 has a high voltage stress of the switches.Fig. 13 Comparing the voltage stress of the switches of the converters versus duty cycle.

Figure 14 shows the voltage stress of the diodes versus duty cycle. According to this figure, the voltage stress of the diodes D1 and D2 of the proposed converter is equal to the voltage stress of the diode D1 of the converters 12,17,21,22,24, the diodes D1 and D4 of the converter 18, the diodes D1 and D2 of the converters 20 and 25. Additionally, the voltage stress of the diode D2 of the converter 17 is the same as that of the diodes D2 and D5 of the converter 18, the diode D3 of the converter 21, and the diode D2 of the converter 24. The voltage stress of the diode D3 of the converter 18 is also equal to the voltage stress of the diode D2 of the converters 21 and 22. Although the voltage stress of the diode D3 of the proposed converter is high, it should be noted that the proposed converter has a relative superiority in terms of voltage gain and structural features compared to the other mentioned converters except the converter 12. The voltage stress of the diodes D1 and D2 of the proposed converter is less or equal to the voltage stress of the diodes of other converters in a duty cycle greater than 50%.Fig. 14 Comparing the voltage stress of the diodes of converters versus duty cycle.

Current stress comparison of semiconductor devices

Figure 15 shows the current stress of the switches of the proposed and compared converters. Observably, the current stress of the switch S2 in the proposed converter matches the current stress of the switch S2 in converters 17 and 22. Moreover, the current stress of another switch in the proposed converter deviates from the current stress observed in the switches of the other compared converters. According to Fig. 15, the current stress of the switch S2 in the proposed converter and switch S2 of the converters 17 and 22 is better than the current stress of the other converters. The current stress of switch S1 of the suggested topology is also within an acceptable range compared to the other converters according to Table 1.Fig. 15 Comparing the current stress of the switches of the converters versus duty cycle.

In Fig. 16, the current stress of the diodes of the proposed converter is juxtaposed with that of the aforementioned converters. In this comparison, the current stress of the diodes D1 and D2 of the proposed converter is the same as the diode D1 of the converter 17, the diodes D1 and D3 of the converter 21 and the diode D1 of the converter 22. Likewise, the current stress of the diode D3 in the proposed converter matches the current stress observed in the diodes D2 and D3 of the converter 12 and the diode D2 of the converters 17 and 22. In the converter 18, the current stress of the diodes D3 and D4 is also equal. The current stress of the diodes D1 and D2 of the converter 20 is also equal to the current stress of the diode D4 of the converters 25. Additionally, the converter 21 diode D1 current stress is the same as that of the diode D3 of the converter 25. The current stress of the diodes D1 and D2 of the converter 25 is also equal. Evidently, the current stress of the diodes of the proposed converter falls within an acceptable range in comparison to the other referenced converters.Fig. 16 Comparing the current stress of the diodes of the converters versus duty cycle.

Small signal modeling of the proposed converter

This section discusses the small signal modeling of the proposed converter. According to the small signal method, the state variables include the current of the inductors iL1(t), iL2(t) and iL3(t), the voltage of the capacitors vC1(t), vC2(t), vC3(t) and vCo(t), the duty cycle d(t) and input voltage vi(t), consisting of two components: DC value (X) and disturbances (x^). Therefore, for the proposed converter, the equations are as follows:41 iL1(t)=IL1+i^L1(t)iL2(t)=IL2+i^L2(t)iL3(t)=IL3+i^L3(t)vC1(t)=VC1+v^C1(t)vC2(t)=VC2+v^C2(t)vC3(t)=VC3+v^C3(t)vCo(t)=VCo+v^Co(t)d(t)=D+d^(t)vi(t)=Vi+v^i(t)withi^L1(t)≪IL1i^L2(t)≪IL2i^L3(t)≪IL3v^C1(t)≪VC1v^C2(t)≪VC2v^C3(t)≪VC3v^Co(t)≪VCod^(t)≪Dv^i(t)≪Vi

By substituting Eq. (41) into Eqs. (1)–(4), the small-signal state equations are obtained as Eq. (42).42 L1di^L1(t)dt=-(1-D)v^C1(t)+Vi1-Dd^(t)+v^i(t)L2di^L2(t)dt=Dv^C1(t)+Dv^C2(t)-(1-D)v^C3(t)+2Vi(1-D)2d^(t)L3di^L3(t)dt=Dv^C1(t)+Dv^C2(t)+Dv^C3(t)-v^Co(t)+2Vi(1-D)2d^(t)C1dv^C1(t)dt=1-D2i^L1(t)-Di^L2(t)-Di^L3(t)-2DViRo(1-D)4d^(t)C2dv^C2(t)dt=1-D2i^L1(t)-Di^L2(t)-Di^L3(t)-2DViRo(1-D)4d^(t)C3dv^C3(t)dt=(1-D)i^L2(t)-Di^L3(t)-2DViRo(1-D)3d^(t)Codv^Co(t)dt=i^L3(t)-1Rov^Co(t)

Matrices A, B, C and D are obtained by simplifying Eq. (42) and comparing it with Eq. (43), in the form of Eqs. (44) to (47).43 x^=Ax+Buy=Cx+Du

44 A=000-1-DL1000000DL2DL2-1-DL20000DL3DL3DL3-1L31-D2C1-DC1-DC100001-D2C2-DC2-DC2000001-DC3-DC30000001Co000-1RoCo

45 B=ViL1(1-D)2ViL2(1-D)22ViL3(1-D)2-2DViRoC1(1-D)4-2DViRoC2(1-D)4-2DViRoC3(1-D)30

46 C=0000001

47 D=0

By performing the Laplace transform on Eq. (43), the control-to-output transfer function of boost and buck modes is obtained as Eqs. (48) and (49).48 Gvd-boost(s)=v⌢o(s)d⌢(s)=2.424e9s4-2.629e11s3+1.217e16s2-3.627e17s+7.826e21s6+15000s5+1.147e8s4+5.224e11s3+1.443e15s2+2.247e18s+1.517e21

49 Gvd-buck(s)=v⌢o(s)d⌢(s)=9.47e8s4-2.163e11s3+9.413e15s2-5.798e17s+1.002e22s6+12604s5+7.36e7s4+2.537e11s3+5.257e14s2+6.084e17s+3.044e20

As can be seen in Eq. (50), the proposed controller includes a real pole (a = 14,000) and a coefficient equal to 1148. The Bode diagram with the presence of the compensator in both boost and buck modes is shown in Fig. 17.50 GC=K(s+a)

Fig. 17 Bode diagram of Gvd(s): (a) boost mode; (b) buck mode.

The Bode diagram based on theoretical calculations without compensator and with adding compensator is shown in Fig. 17. Figure 17a shows the Bode diagram in boost mode for duty cycle (D = 0.5) and load (R = 97.82 Ω). Also, Fig. 17b has drawn the Bode diagram in buck mode for (D = 0.2) and load (R = 3.15 Ω). From the figure, it is clear that both boost and buck modes in the mode without compensator, the values of gain margin (GM) and phase margin (PM) are not in the appropriate control range. As a result, the system under study does not have proper stability when a change in duty cycle occurs. Using MATLAB software SISOTOOL and considering the appropriate range of gain margin (at least 5 dB) and phase margin (between 30 and 80 degrees), the suitable controller is obtained as follows.

By using the controller, GM and PM in the boost mode are equal to 7.64 dB and 33.3 degrees, respectively. Similarly, the GM and PM of the buck mode are 13.8 dB and 80 degrees, respectively. It follows that the system under study is stable in spite of the disturbance of changes in duty cycle. Figure 18 shows the block diagram of the proposed converter control system considering the desired gain margin and phase margin.Fig. 18 Block diagram of the proposed converter control system.

The performance of the proposed converter in closed-loop conditions has been investigated in two scenarios including input voltage instantaneous change and output load sudden change. In the first scenario, the input DC voltage is reduced linearly from 30 to 10 V in the period of [0.3–0.5] seconds. In this situation, the output voltage reference value is set to 20 V and the goal is to stabilize the output voltage at 20 V. According to Fig. 19, the output voltage is well stabilized at 20 V and the proposed converter closed-loop system has worked correctly for a wide range of input voltage changes. In a time interval less than 0.4 s, the converter operates in the buck mode and for a time interval greater than 0.4 s, the converter operates in the boost mode. Therefore, the transition from buck to boost mode has been done without any problems. The duty cycle of the switches in this scenario is shown in Fig. 19b. The duty cycle has updated its value with steps of 0.05 when necessary. At the moment when this change in the duty cycle occurs, a negligible ripple is observed in the output voltage, which can be ignored. In Fig. 19c, the input and output current of the converter can be seen. Considering that the output load is constant and receives 3 A per 20 V output voltage, the input current should be increased by gradually decreasing the input voltage. According to this figure, the input current is gradually and continuously increased and the power balance between input and output is established.Fig. 19 The closed-loop control performance of the proposed converter for changing the input voltage.

In the second scenario, the output load changes suddenly and then the performance of the closed loop control system is evaluated in this condition. In this scenario, the input voltage is 10 V and the closed-loop control sets the output voltage to 20 V. Therefore, the converter works in boost conditions. At 0.3 s, the output load resistance has decreased by 50%, which leads to a 50% increase in the output current from 2 to 3 A. At the moment of 0.4 s, the output resistance has increased by the same amount and the output load current decreases from 3 to 2 A. According to the results presented in Fig. 20, the closed-loop control system has worked correctly in this condition and the output voltage has been stabilized at 2 0 V. For this scenario, the waveform of the input and output current is shown in Fig. 20a, the duty cycle of the switches in Fig. 20b and the input and output voltage of the converter is shown in Fig. 20c.Fig. 20 The closed-loop control performance of the proposed converter for instantaneous change of the output load.

Simulation and experimental results

Simulation results

Based on the parameters in Table 2, simulation has been conducted in Simulink MATLAB to verify the performance of the buck–boost converter. The simulation analysis of the proposed converter has been performed in two boost and buck modes in CCM mode, and the results for both modes are presented in Fig. 21. The evaluated output power for the boost and buck modes corresponds to 60 W and 40 W, respectively. Also, the power switches are controlled simultaneously on a duty cycle of 50% for boost mode and 20% for buck mode. Consequently, the outcomes were derived under practical circumstances, considering the impact of parasitic parameters. Therefore, the small difference between calculation and simulation results is negligible.Table 2 Proposed converter parameters.

Buck mode	Boost mode	Parameters	
20 V	20 V	Input voltage	
12.5 V	80 V	Output voltage (ideal)	
10.2 V	75.84 V	Output voltage (real)	
40 W	60 W	Output power	
50 KHz	50 KHz	Switching frequency	
3.16 Ω	95.86 Ω	Output load	
0.2	0.5	Duty cycle	
IRFP260N	IRFP260N	MOSFETs	
MBR20150CT	MBR20150CT	Diodes (D1, D2)	
MUR1660CT	MUR1660CT	Diode (D3)	
200 μH	200 μH	Inductor (L1)	
2 mH	2 mH	Inductors (L2, L3)	
220 μF	220 μF	Capacitors (C1, C2)	
330 μF	330 μF	Capacitor (C3)	
150 μF	150 μF	Capacitor (Co)	

Fig. 21 The waveforms of the simulation results of the proposed converter: (a) boost mode; (b) buck mode.

The output voltage and output current, the current of inductors, the voltage of capacitors, the voltage of diodes, the voltage of switches and the gate signals of switches are shown in Fig. 21. The input voltage of the converter in boost mode changes from 20 to 75.84 V with positive polarity, considering the duty cycle of 50%, which is equal to 80 V in the ideal state and based on theoretical calculations. The output current of the converter in boost mode is approximately equal to 0.79 A and is close to the ideal output current value equal to 0.83 A. It is worth mentioning that a difference of about 5% between the results of real conditions and ideal conditions is common and if the elements with lower parasitic values are used in the converter, this difference will be less. According to Fig. 21a, the average current of inductors L1, L2, and L3 is equal to 3.1 A, 0.8 A, and 0.8 A, respectively, which confirm the theoretical calculations made in Eq. (15). The voltage of capacitors C1, C2, C3 and Co from Fig. 21a, is equal to 38.6 V, 38.6 V, 75.84 V and 75.84 V, respectively, and these values correspond to Eqs. (8) to (10). Furthermore, according to Fig. 21a, the voltage of diodes D1, D2, and D3 is equal to 40 V, 40 V, and 160 V, respectively, and these values also correspond to the voltage stress on diodes according to Table 1. The voltage of switches S1 and S2 in Fig. 21a is equal to 40 V and 120 V, respectively, which confirms the theoretical calculations compared to the voltage stress of switches in Table 1.

As indicated in Fig. 21b, the output voltage of the converter in the buck mode, considering a duty cycle of 20%, approximates 10.2 V, which closely aligns with the voltage in the ideal scenario, namely 12.5 V. The output current of the converter in buck mode according to Fig. 21b is equal to 3.92 A and in the ideal state it is equal to 3.95 A, which the closeness of these values shows the correctness of the theoretical calculations. The average current of inductors L1, L2 and L3 in Fig. 21b is equal to 2.5 A, 0.98 A and 3.94 A, respectively, which confirms the correctness of theoretical calculations compared to Eq. (15). The voltage of capacitors C1, C2, C3 and Co in Fig. 21b is equal to 23.9 V, 23.9 V, 10.35 V and 10.21 V, respectively, which corresponds to Eqs. (8)–(10). The voltage of diodes D1, D2 and D3 is equal to 24 V, 24 V and 60 V according to Fig. 21b, which also corresponds to the voltage stress of diodes according to Table 1. Moreover, the voltage of switches S1 and S2 is shown in Fig. 21b is almost equal to 25 V and 36 V, which is confirmed by the theoretical calculations compared to the voltage stress of switches in Table 1.

Experimental results

As can be seen in Fig. 22, to validate the precision of the simulation outcomes and the theoretical computations, a laboratory prototype was constructed. The results of the experimental prototype of the proposed converter are shown in Figs. 23 and 24. These figures exhibit the waveforms of currents and voltages across various components of the proposed converter within the laboratory setting, showcasing both the boost and buck modes. In Fig. 23, the results for the boost mode at duty cycle 50% are presented. Figure 23 shows the buck mode for some converter waveforms at duty cycle 20%. Figures 25 and 26 also show the output voltage and current in two boost and buck modes, respectively. The parasitic parameters of the equipment used in the practical circuit are similar to those introduced in Sect. (2.5.A).Fig. 22 Prototype of the proposed converter.

Fig. 23 Experimental results: boost mode.

Fig. 24 Experimental results: buck mode.

Fig. 25 Experimental results: output voltage/current in boost mode.

Fig. 26 Experimental results: output voltage/current in buck mode.

The average current of inductors L1, L2 and L3 in Fig. 23 is equal to 3.1 A, 0.8 A and 0.8 A, respectively, which corresponds to Eq. (15). The voltage of capacitors C1, C2 and C3 in Fig. 23 is equal to 38 V, 35 V and 75 V, respectively, which is also consistent with Eqs. (8) to (10). The voltage of diodes D1 and D2 in Fig. 23 is equal to 38 V and 39 V, respectively, which corresponds to the voltage stress of diodes in Table 1. The voltage of switches S1 and S2 in Fig. 23 is equal to 40 V and 114 V, respectively, which corresponds to the voltage stress of switches in Table 1.

The average current of inductors L1, L2, and L3 in Fig. 24 is equal to 2.5 A, 1 A, and 4 A, respectively, which confirms the correctness of the calculations compared to Eq. (15). The voltage of capacitors C1, C2, and C3 in Fig. 24 is equal to 24 V, 24 V, and 10.1 V, respectively, and comparing it with Eqs. (8)–(10), confirms the correctness of the theoretical calculations. The voltage of diodes D1 and D2 in Fig. 24 is equal to 24 V and 26 V, respectively, which corresponds to the voltage of diodes in Table 1. The voltage of switches S1 and S2 in Fig. 24 is equal to 27 V and 36 V, respectively, which is consistent with the voltage stress of switches in Table 1.

The output voltage and output current depicted in Fig. 25, under the boost mode, correspond to 76 V and 0.78 A, respectively, aligning with the theoretical calculations in the ideal condition. Similarly, the output voltage and output current showcased in Fig. 26, during the buck mode, are recorded as 10 V and 3.9 A, respectively, harmonizing with the theoretical computations under ideal circumstances.

Conclusion

This paper presents a non-inverting DC–DC buck–boost converter based on a modified boost converter and ZETA converter, which has the advantages of both converters such as continuous input/output current and positive polarity of the output voltage. The voltage conversion ratio of this topology is semi-quadratic and encompasses an extensive range of conversion ratios. The continuous output current of this converter renders it suitable for applications in renewable energy systems and industrial settings. The simultaneous operation of the switches in the converter results in a straightforward control mechanism. The continuity of input and output currents leads to a reduction in input current and output voltage ripples. Comparison of the ideal voltage gain of the converter with other similar models underscores the superiority of the proposed converter. The voltage/current stress of the switches and diodes as well as the introduced topology efficiency and its comparison with other structures are presented. The comparison results show the superiority of the suggested converter over other topologies in most cases. The small signal modeling and closed-loop control were also presented. The simulation results in two boost and buck modes using the Simulink environment of MATLAB software confirm the theoretical calculations. Finally, a 40 ~ 60W, 20 to 76 V for boost mode and 10 V for buck mode prototype are implemented in the laboratory to verify the simulation results and the relationships obtained from the theoretical analysis.

Author contributions

All authors reviewed the manuscript. M.H. designed and performed all the experiments, data analysis, documentation and supervision. M.H. performed the experiment, data analysis, and documentation. M.E.A. performed the data analysis and supervision.

Data availability

All data generated and analyzed during the current study are available from the corresponding author upon reasonable request.

Competing interests

The authors declare no competing interests.

Publisher's note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
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