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10.1186/s11671-024-04096-4
Research
FS-iTFET: advancing tunnel FET technology with Schottky-inductive source and GAA design
Lin Jyi-Tsong jtlin@ee.nsysu.edu.tw

Tai Wei-Heng
https://ror.org/00mjawt10 grid.412036.2 0000 0004 0531 9758 Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, 80424 Taiwan, ROC
4 9 2024
4 9 2024
12 2024
19 1 14026 6 2024
26 8 2024
© The Author(s) 2024
2024
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In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling heterojunction channel. The overlapping gate and source contact regions create a strong and uniform electric field in the channel. Furthermore, the metal–semiconductor Schottky junction in the intrinsic source region induces the required carriers without the need for doping. This innovative design achieves both a steeper subthreshold swing (SS) and a higher ON-state current (ION). Using calibration-based simulations with Sentaurus TCAD, we compare the performance of three newly designed device structures: the conventional Nanosheet Tunnel Field-Effect Transistor (NS-TFET), the Nanosheet Line-tunneling TFET (NS-LTFET), and the proposed FS-iTFET. Simulation results show that, compared to the traditional NS-TFET, the NS-LTFET with its full line-tunneling structure improves the average subthreshold swing (SSAVG) by 19.2%. More significantly, the FS-iTFET, utilizing the Schottky-inductive source, further improves the SSAVG by 49% and achieves a superior ION/IOFF ratio. Additionally, we explore the impact of Trap-Assisted Tunneling on the performance of the three different integrations. The FS-iTFET consistently demonstrates superior performance across various metrics, highlighting its potential in advancing tunnel field-effect transistor technology.

Keywords

Forkshape
Nanosheet
Schottky barrier
Tunnel field-effect transistor (TFET)
Gate ALL around (GAA)
Heterojunction
Metal–semiconductor interface
Subthreshold swing (SS)
Line tunneling
Ministry of Science and Technology of Taiwan, R.O.C.MOST109-2221-E-110-018-MY3 MOST109-2221-E-110-018-MY3 Lin Jyi-Tsong Tai Wei-Heng issue-copyright-statement© Springer Science+Business Media, LLC, part of Springer Nature 2024
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pmcIntroduction

As semiconductor devices continue to be scaled down and the demand for Internet of Things (IoT) technology and artificial intelligence applications increases, reducing overall power consumption has become a critical and urgent research topic [1]. The Tunnel Field Effect Transistor (TFET) operates based on the minority carrier injection mechanism through Band-To-Band Tunneling (BTBT). Unlike the thermionic emission current in MOSFETs, BTBT current in TFETs results in a more abrupt change in channel potential, offering superior switching characteristics and significantly lower Subthreshold Swing (SS). This makes TFETs highly promising for low-power applications [2]. Given the physical limitations of single-crystalline MOSFETs, TFETs have the potential to achieve subthreshold swing values much below the thermal limit of 60 mV/dec at room temperature [2–4]. However, the practical application of TFETs is hindered by several challenges such as lower ON-state current (ION) due to minority carrier tunneling and unstable non-ideal effects like Trap-Assisted Tunneling (TAT) and ambipolar behavior, which need to be addressed [5–10].

Enhancing on-current and switching performance can be achieved by using heteromaterial and other methods. Compared to a fully silicon-based structure, introducing a heterojunction between the source and channel areas and using a narrow bandgap material in the source region can shorten the tunneling distance and provide better band-to-band tunneling behavior [11, 12]. Additionally, incorporating a drain region with a wider bandgap material can effectively reduce the device's leakage current, thereby significantly improving the ON-state/OFF-state current (ION/IOFF) ratio [6]. In traditional P-I-N TFETs, band-to-band tunneling (BTBT) occurs primarily at the interface corner between the source and channel areas, known as point tunneling. This type of tunneling, which is parallel to the channel, is influenced by the local electric field. However, the electric field within the channel is typically continuously changing with channel position, leading to a smaller corner tunneling region and significantly limiting the device's switching performance. In contrast, utilizing tunneling perpendicular to the channel, known as line tunneling, provides a controllable and expandable tunneling area [13]. Combining this with a metal–semiconductor Schottky source can form a depletion region at the interface, creating the necessary carrier inversion layer to achieve a p–n junction-like effect [6, 14], and establishing a larger and more uniform electric field within the channel. This approach is highly beneficial for enhancing the ION of TFETs, as higher current drive facilitates faster switching speeds and better device performance.

As low-power and high-speed devices, TFETs rely significantly on gate-over-channel controllability. Recent studies have demonstrated that integrating Gate-All-Around (GAA) [15, 16] nanosheet structures with TFETs offers excellent potential in terms of scalability [17] and enhanced switching characteristics, achieving an ION/IOFF ratio of ≧105 and an average subthreshold swing (SSAVG) of less than 45 mV/dec [18–21]. Furthermore, due to their vertical-tunneling mechanisms, line-tunneling TFETs can significantly increase the total effective tunneling area by utilizing multiple nanosheets.

Nowadays, the term "technology node" symbolizes the overall advancements in manufacturing processes, including factors such as transistor density and performance, rather than a specific feature size, such as fin-width or gate length. In this paper, our design focuses on the channel thickness (tSi), the gate/source overlapping channel length (LG), the channel width (W), and the number of nanosheets, as shown in Table 1. This enhances the efficiency and performance of our integration by optimizing the total tunneling processes. This results in superior efficiency and performance, as the increased overlap area between the source and the gate directly contributes to better device characteristics. Additionally, by integrating these advantages with a Schottky inductive source, it is possible to enhance the ION while maintaining good gate controllability over the channel current.Table 1 Device parameters of FS-iTFET used for simulations

Device parameters		
Germanium Source Thickness(tGe)	3 nm	
Silicon Channel Thickness(tSi)	3 nm	
Gate Oxide Thickness (tOX)	3 nm	
Gate Length (LG)	50 nm	
Inner Oxide Length (LIO)	10 nm	
Channel Heigh (H)	18 nm	
Channel Width (W)	20 nm	
Gate Oxide to Drain Contact Length	25 nm	
Drain Doping Concentration (Phosphorus)	5 × 1018 cm−3	
Germanium Source Doping Concentration	Intrinsic	
Silicon Channel Doping Concentration	Intrinsic	
Gate Work Function	4.05 eV	
Schottky Barrier at Source	0.7 eV	

Using calibration-based simulations with Sentaurus TCAD, we propose and integrate a novel Forkshape nanosheet inductive TFET (FS-iTFET) and compare its performance aspects with two newly designed integrations based on the traditional P-I-N TFET structure and the conventional line TFET: the Nanosheet TFET (NS-TFET) and the Nanosheet Line-Tunneling TFET (NS-LTFET). Notably, our newly designed NS-LTFET employs complete line tunneling between the channel layer and the heavily doped source.

This paper provides a detailed comparison of the current characteristics, subthreshold behavior, energy bands, and TAT induced by interface traps between heterojunctions [9] of the three integrations. Additionally, common ambipolar effects [5] in TFETs and the impact of different materials on FS-iTFET are discussed in detail. Section 2 describes the device structure and parameter sets for the FS-iTFET, NS-TFET, and NS-LTFET used for comparison, along with the simulation calibration strategy and process schematics. The simulation results and discussion, including the impact of various non-ideal effects, are thoroughly detailed in Sect. 3.

Device structure and simulation strategy

Device structure and parameters used for simulations

The following discussions on device structures primarily utilize n-type TFETs as the main comparative structures. By altering doping levels and Schottky barrier heights, p-type TFETs can be achieved for further complementary TFET (cTFET) engineering [18]. In Fig. 1, our proposed FS-iTFET and two integrated structures for comparison are shown. The 3D structure of individual layer FS-iTFET is depicted in Fig. 1a, while the cross-section, and device parameters are shown in Fig. 1d, and Table 1, respectively. As discussed in the introduction, FS-iTFET uses a narrow bandgap germanium source to enhance tunneling rates [12] and a silicon channel and drain with a wider bandgap compared to the source to reduce leakage current [6]. At the FS-iTFET source metal–semiconductor junction, a Schottky barrier height (SBH) [14] of 0.7 eV is employed to induce sufficient carrier (hole) concentration in the intrinsic germanium source. The source metal electrode plate fully covers the gate region, ensuring a strong and uniform vertical electric field across the entire tunneling region. The inner oxide layer between the source and drain is designed to suppress point tunneling near the drain/channel region and also to block potential leakage currents that might arise due to the proximity of the drain and source.Fig. 1 Schematic device structures of a the 3-D structure of Forkshape Inductive Tunnel Field-Effect Transistor (FS-iTFET), b the cross-sectional view of traditional PIN Nanosheet TFET (NS-TFET), c the cross-sectional view of Nanosheet Line-tunneling TFET (NS-LTFET), and d the cross-sectional view of single stack FS-iTFET for performance comparison. Where, the cutlines A–A’, C–C’, and E–E’ are set 1 nm under the Silicon Channel/HfO2 interface; the cutlines B–B’, D–D’, and F–F’ are set 5 nm next to the left Spacer/Silicon Channel interface

Figure 1b, c depict two novel integrations derived from conventional PIN TFET and traditional line tunneling TFET, namely NS-TFET and NS-LTFET. The primary distinction between NS-TFET and NS-LTFET lies in their respective tunneling mechanisms: NS-TFET is predominantly governed by point tunneling, whereas NS-LTFET is characterized by line tunneling. This comparison aims to elucidate the influence of point and line tunneling on the current performance of TFETs.

And the primary difference between our proposed FS-iTFET and NS-LTFET lies in the composition and doping of the source region. In scenarios where line tunneling is dominant, FS-iTFET replaces the traditionally highly doped source with a Schottky-induced intrinsic source. The intrinsic source region helps prevent the phenomenon where heavy doping concentrations cause the depletion region to be narrowed, subsequently reducing the influence of the Schottky barrier [14].

To ensure a precise comparison of current characteristics in the subsequent discussion in Sect. 3, the NS-TFET and NS-LTFET are designed with identical doping concentrations and gate lengths in each region. Furthermore, the NS-LTFET and FS-iTFET share the same gate length and channel thickness.

Multi-step calibrations for a specific model

To enhance the accuracy and credibility of subsequent simulation results, the calibration outcomes for different physical models are shown in Fig. 2a, b. The main model and material parameters used are listed in Table 2, while other parameters are set to default values. The two-step calibration for specific models allow the simulation results to more closely reflect the actual physical phenomena of the devices.Fig. 2 Calibrations for a carrier transport, mobility, and quantum correction model [22], and b BTBT and SRH-TAT model [23]

Table 2 Model parameters used for simulations

Parameters	Si	Ge	
ε	11.7	16.2	
Aind	3.29 × 1015 cm−3 s−1	1.67 × 1015 cm−3 s−1	
Bind	23.8 MV/cm	6.55 MV/cm	
P	2.5	2.5	
F0	1 V/cm	1 V/cm	
mt	0.087	0.032	
Et	0 eV	0 eV	
τmax	Electrons:1 × 10–5 s	 Electrons:1 × 10–5 s	
	Holes: 3 × 10–6 s	 Holes: 3 × 10–6 s	

In Fig. 2a, the NSFET in L. Cai et al. [22] is structurally highly consistent with our nanosheet. We calibrated the hydrodynamic carrier transport model and the mobility model, among others, to ensure accuracy. Additionally, the activation of the high-field saturation of Extended-Canali and velocity saturation models considered the velocity saturation in the high electric field channel regions due to the small device dimensions [24]. For nanoscale device channels, the mobility cannot be accurately expressed using conventional field-dependent interface models due to geometric quantization [25]. In such cases, the thin-layer mobility model is actively employed.

As the band-to band generation rate is concerned,1 GBTBT=AindFF0Pexp-BindF

where P = 2 for the direct tunneling process, and P = 2.5 for phonon-assisted tunneling process; the parameter Aind, Bind are the indirect Kane parameters and F is the electric field applied [24, 26].

For TFETs, band-to-band tunneling (BTBT) primarily governs their main current characteristics. The Si/Ge heterojunction GAA structure TFET [23] used in Fig. 2b is well-suited for calibrating the BTBT model for the FS-iTFET proposed in this paper. To accurately simulate the phonon-assisted tunneling behavior of the silicon/germanium heterojunction TFET, a dynamic non-local path indirect BTBT model is employed. The BTBT generation rate described by Eq. (1), and the parameter set includes the tunneling mass (mt) as shown in Table 2. Doping-dependent and temperature-dependent Shockley–Read–Hall (SRH) recombination, along with the dynamic non-local Schenk TAT model, are also applied, with maximum carrier lifetimes (τmax) and midgap trap energy level (Et) as shown in Table 2. The dynamic non-local Schenk TAT model provides more accurate simulation results for heterojunction devices [24]. To enhance simulation accuracy, the band gap narrowing of the Jain-Roulston model and the Auger recombination model, both using default parameters, are also enabled.

It should be noted that the default potential parameter density gradient quantum correction model is enabled in all calibrations. This model may be somewhat inadequate in calculating the bandgap expansion caused by quantization, leading to a reduction in IDS [27, 28]. The impact of this on device characteristics and the related discussion will be explained in Sect. 3.

Process flow for FS-iTFET

The cross-sectional process schematic diagrams for FS-iTFET are illustrated in Fig. 3a–l. The steps depicted in Fig. 3a–k involve the construction of a single-sided structure, while Fig. 3l represents the final symmetrical device structure. Similar to recent advancements in nanosheet processes [29], FS-iTFET employs a stacked architecture and etches out fins to complete the subsequent structure, as shown in Fig. 3a. Following the formation of the inner spacer [30], a selective wet etching process [31, 32] is employed on the silicon layer, creating a fork-shaped structure with a dummy gate that fully encapsulates the SiGe layer as illustrated in Fig. 3b–d. Intrinsic germanium and silicon are deposited as the source and channel layer, respectively. Multilayer spacers are then used to define different regions of the device, facilitating the subsequent etching process, as depicted in Fig. 3e–f.Fig. 3 a–l Cross-sectional views of key fabrication process steps for FS-iTFET

In Fig. 3g, the initial step involves defining a photomask and using ion bombardment to expose the internal SiGe layer. Following this, wet etching is used to shorten the SiGe and Ge layers to a specific length. Subsequently, inner spacers are utilized to form an inner oxide isolation. The process continues in Fig. 3h–i by depositing an epitaxial (epi) drain layer through in-situ doping. After removing the Si3N4 layer, the High-K Metal Gate (HKMG) process [29] is employed to complete the gate region. In Fig. 3j, a defined photomask is used to expose the internal SiGe layer through ion bombardment. The device is then completed by using the Replacement Metal Gate (RMG) [33] process to introduce source metal on germanium and form a Schottky contact, as depicted in Fig. 3k–l.

FS-iTFET exhibits considerable scalability, and its potential for device miniaturization and integration with existing CMOS technology [29, 30] makes it a promising candidate for future development. However, it also faces significant manufacturing challenges compared to traditional technologies. Overcoming these challenges will require advancements in materials, processes, and equipment, as well as substantial investment. The more complex manufacturing processes and stricter tolerances may pose challenges in achieving similar yield and reliability during the initial stages.

It is worthwhile noting that nowadays, the feature size of ITRS is determined by the fin width rather than the gate length. The FS-iTFET can be easily implemented through fin-like and nanosheet integrations, making it compatible with recent 3 nm and 2 nm technology nodes.

Results and discussion

Impact of line-tunneling and Schottky inductive structure on device behavior

In the following discussion, the current characteristics and subthreshold performance of FS-iTFET, NS-TFET, and NS-LTFET are compared in detail. The gate work function of all devices is set to 4.05 eV, which means each device may have different threshold voltages before normalization. It should be noted that the interface trap density between the oxide and semiconductor is taken from [26, 34] while the interface traps between heterojunctions will be discussed in depth later.

As shown in Fig. 4a–d and Table 3, FS-iTFET demonstrates the best performance in current characteristics and subthreshold behavior. Compared to the conventional point tunneling-dominated NS-TFET, NS-LTFET exhibits a 19.2% improvement in the average subthreshold swing (SSAVG), a higher ION, and a slightly improved ION/IOFF ratio. The FS-iTFET, using a Schottky-induced source structure, shows a 49% improvement in SSAVG over the heavily doped source structure of NS-LTFET, offering the highest ION, the best ION/IOFF ratio, and a subthreshold swing (SS) below 60 mV/decade.Fig. 4 Performance comparison of NS-TFET, NS-LTFET, and FS-iTFET: a Transfer characteristics for different structures, b Corresponding subthreshold swing (SS) versus drain current, c Corresponding transconductance (gm) versus gate voltage, d SS behavior and ION/IOFF comparison of different structures

Table 3 the ion, IOFF and SSAVG of the proposed device structure

Stracture	FS-iTFET	NS-LTFET	NS-TFET	
ION (A/μm)	6.4 × 10–5	3.29 × 10–5	4.6 × 10–6	
IOFF (A/μm)	2.38 × 10–14	2.18 × 10–12	3.1 × 10–13	
ION / IOFF	2.69 × 109	1.51 × 107	1.48 × 107	
SSAVG (mV/dec)	21	41.2	51	

Energy band diagrams and tunneling behavior

Figure 5a–f display the device cross-sectional energy band diagrams of NS-TFET, NS-LTFET, and FS-iTFET under different operating conditions. The cutlines of the energy band diagrams are shown in Fig. 1b–d. Specifically, the cutlines in Fig. 5a, c, e are perpendicular to the gate electric field, while the cutlines in Fig. 5b, d, f are aligned with the gate electric field direction. From the energy band diagrams, it is evident that in the ON state of the devices, the tunneling direction of NS-TFET differs from that of NS-LTFET and FS-iTFET. Figure 5a, b show that NS-TFET is entirely dominated by point tunneling, with tunneling occurring only in the direction perpendicular to the gate electric field. On the other hand, Fig. 5c–f show that the ION of NS-LTFET and FS-iTFET is completely dominated by line tunneling, with tunneling occurring only in the direction aligned with the gate electric field. Thanks to their tunneling direction, line tunneling devices have a significant advantage in controlling the number of tunneling carriers within the channel.Fig. 5 Energy band diagrams of NS-TFET, NS-LTFET, and FS-iTFET in different operational states: a, b Energy band diagrams of NS-TFET along cutlines A–A’ and B–B’, c, d Energy band diagrams of NS-LTFET along cutlines C–C’ and D–D’, e, f Energy band diagrams of FS-iTFET along cutlines E-E’ and D-D’

Band-to-band generation and leakage current

Figure 6 illustrates the band-to-band generation behavior of three devices, revealing that the FS-iTFET and NS-LTFET exhibit better uniformity and concentration of band-to-band generation across the entire channel compared to the conventional NS-TFET. This suggests that the generation region of tunneling carriers nearly matches the length of the gate/source overlap region. This characteristic demonstrates that the line tunneling structure can enhance the total tunneling area by adjusting the gate/source overlap length (LG) while maintaining the same channel thickness (tSi), thereby achieving superior current characteristics [35].Fig. 6 Cross-sectional comparison of the electron band-to-band tunneling (BTBT) generation rate for NS-TFET, NS-LTFET, and FS-iTFET

It is noteworthy that in conventional stacked nanosheet MOSFETs, the current drive is proportional to both the W/L ratio and the number of stacked nanosheets. In contrast, the current drive of our proposed fork-shaped nanosheet iTFET is proportional to both the total effective area (L × W) and the number of stacked nanosheets.

Moreover, unlike NS-TFET and NS-LTFET, FS-iTFET exhibits minimal band-to-band generation in the off-state, effectively controlling leakage current.

Induced carrier distribution and electric field

Compared to the NS-LTFET, which uses heavy doping and electrode contact at the source edge, the FS-iTFET employs intrinsic doping in the source region and covers the entire gate area with a Schottky contact metal plate to induce a carrier layer. Figure 7a shows the induced non-uniform hole carrier concentration distribution. Additionally, Fig. 7b reveals that the FS-iTFET has a larger and more uniform electric field within the channel compared to the NS-LTFET, resulting in superior band-to-band tunneling performance [13].Fig. 7 a Hole density along cutline I-I’ in a FS-iTFET, b Electric field diagram along the silicon channel for NS-LTFET and FS-iTFET, respectively

In summary, due to the fully line-tunneling behavior and the gate region being covered by the source metal plate, the FS-iTFET forms a strong and uniform electric field in the whole line-tunneling region, thereby outperforming the traditional PIN structure in terms of subthreshold behavior. Additionally, the rapid switching characteristics of the Schottky-junction behavior enhance the device's response speed, which is of particularly important for high-speed applications. The intrinsic doping used in the source region maximizes the effect of the Schottky barrier [14], and the FS-iTFET's doping process requires in-situ doping only in the drain region, thereby reducing the thermal budget during the manufacturing process. However, this technology also has certain limitations, such as reliability issues and relatively high manufacturing precision requirements. In practical applications, it is necessary to balance these advantages and limitations.

Impact of Schottky Barrier height on BTBT

Based on the analysis of Fig. 8, we observe the impact of different Schottky Barrier Heights (SBH) on the performance of FS-iTFETs. As shown in Fig. 8a, the device's ION/IOFF ratio increases with the rise in source SBH. When SBH = 0.7 eV, the FS-iTFET demonstrates optimal subthreshold performance, achieving the best SS margin being less than 60 mV/dec. Figure 8b further illustrates the influence of SBH on the subthreshold swing. Higher SBH values result in a significant increase in SS margin. Figure 8c, d respectively show the hole density and energy band diagrams corresponding to different SBH values. As SBH increases, the resulting hole density and its gradient become larger and steeper, indicating a proportional relationship between SBH and the induced charge concentration.Fig. 8 a Transfer characteristics of FS-iTFET with different Schottky Barrier Heights (SBH), b Corresponding subthreshold swing (SS) versus drain current, c Corresponding hole density along cutline I-I’, and d Corresponding band diagram along cutline I-I’

This implies that a higher source hole concentration will lead to greater overlap in the energy band diagram, thereby enhancing the BTBT. However, although a high source doping concentration can generate a significant ION, the SS range may not be ideal. Therefore, in practical applications, the optimal SBH should be chosen based on the specific doping concentration to achieve the best performance balance.

Effect of channel and source material and the inner oxide engineering optimization between heterojunctions

Device characteristics can be significantly optimized through the judicious use of heteromaterials, as discussed previously in the introduction. Figure 9 illustrates the impact of different channel and source materials on the current characteristics while maintaining a silicon drain. As shown in Fig. 9a, the germanium homojunction exhibits the highest on-current but suffers from significant leakage and severe ambipolar effects. The device's operation as a switch within the desired operating range can be severely limited due to excessive ambipolar behavior, causing the device to carry significant current even in the off state [5]. The overall current of the silicon homojunction structure is relatively low, with its SS behavior also highly limited. However, using a silicon channel with a germanium source allows for a larger ION while simultaneously reducing leakage current and suppressing ambipolar effects. Moreover, as depicted in Fig. 9b, the subthreshold swing (SS) of the Si/Ge heterojunction exhibits the best SS margin versus drain current, achieving values below 60 mV/dec. Therefore, selecting a wider bandgap silicon channel and a narrower bandgap germanium source provides optimal device characteristics using both silicon and germanium materials.Fig. 9 a Transfer characteristics of FS-iTFET with different channel/source materials, b Corresponding subthreshold swing (SS) versus drain current

The engineering of the inner oxide layer between the germanium source and silicon drain also significantly impacts the current characteristics of the FS-iTFET, as shown in Fig. 10a, b. In the absence of inner oxide engineering between the source and drain, the IOFF of the device approaches 10–7 (A/μm), compared to approximately 4 × 10–14 (A/μm) in the structure with the oxide layer, an increase of nearly six orders of magnitude. Although the device without oxide engineering between the source and drain shows a slight improvement in the ION, optimization is necessary due to the almost uncontrollable leakage current.Fig. 10 a Transfer characteristics of FS-iTFET with and without inner oxide between the source/drain region, b-1 Cross-sectional view of FS-iTFET with inner oxide between the source/drain region, b-2 Cross-sectional view of FS-iTFET without inner oxide between the source/drain region, c, d Energy band diagram of NS-TFET in the OFF-state along cutlines G–G’ and H–H’. Where the cutlines G–G’ and H–H’ are set 1 nm below the silicon channel/germanium source interface

The cross-sectional band diagrams in the device off-state are illustrated in Fig. 10c, d, with the corresponding cutlines shown in Fig. 10b-1, b-2. In the case with inner oxide engineering between the source and drain (Fig. 10c), the bandgap of the oxide layer effectively isolates the energy-band overlap that may occur due to the bandgap difference of heterojunctions (Fig. 10d). Thus, in the off-state of the device, carrier tunneling from the valence band in the source region to the conduction band in the drain region is prevented. The resulting difference in BTBT generation rates is illustrated in Fig. 11, showing a significant difference in the drain area.Fig. 11 Electron band-to-band tunneling (BTBT) generation rate of FS-iTFET with and without inner oxide between the source/drain region

Impact of trap-assisted tunneling by interface traps between heterojunctions

As an ultra-low power consumption and low subthreshold swing device, the TFET can experience significant performance impacts due to material and structural variations, as well as interface traps caused by process defects [9]. Trap-assisted tunneling (TAT) resulting from interface traps has always been a challenging obstacle in TFET performance [8]. While the traps between the oxide layer and the semiconductor have been incorporated into simulations in previous discussions, the impact of interface traps between heterojunctions, as in NS-LTFET and FS-iTFET with a large area of heterojunctions also needs to be addressed. Figure 12a illustrates the transfer characteristics of FS-iTFET in comparison to model differences in the presence of interface traps Nit (Si/Ge) = 1012 cm−3 between silicon and germanium. The results indicate that during device on-state, BTBT dominates the main current behavior, while during the off state, TAT governs the current, making TAT the primary non-ideal effect influencing the OFF-state current. Figure 12b illustrates the variation trend in the current transfer characteristics of FS-iTFET with changes in Nit (Si/Ge). As Nit (Si/Ge) increases, IOFF, which is most severely affected by TAT, also increases. Furthermore, as discussed in [36], temperature is a significant factor that influences TAT. The current characteristics and SS performance with Nit (Si/Ge) = 1012 cm−3 in comparison to different temperatures are depicted in Fig. 12c, d. Despite a slight decrease in on-current with decreasing temperature, the decrease in off-current is substantial. The IOFF decreased by approximately 2.5 orders of magnitude as the temperature dropped from 300 to 200 K. Simultaneously, the margin of SS relative to the drain current also increased significantly.Fig. 12 a Transfer characteristics of FS-iTFET with interface trap density (Nit) between Si/Ge, comparing different models, b Transfer characteristics of FS-iTFET with varying Nit between Si/Ge, c Transfer characteristics of FS-iTFET with Nit between Si/Ge, comparing different temperatures, d Corresponding subthreshold swing (SS) versus drain current at different temperatures

Figure 13 and Table 4 provide a detailed comparison of the transfer characteristics and subthreshold swing performance differences among three devices: NS-TFET, NS-LTFET, and FS-iTFET, under Nit (Si/Ge) = 1012 cm−3. In Fig. 13a, it is observed that, compared to the conventional NS-TFET dominated by point tunneling, the NS-LTFET and FS-iTFET, which are dominated by line tunneling, are more severely affected by TAT, similar to the results described by J.-M. Guo et al. in reference [37]. Additionally, as shown in Fig. 13c and (d), for the three devices compared, the impact of TAT on IOFF is particularly significant compared to ION. As a fully line-tunneling device, the IOFF of FS-iTFET is affected by Nit (Si/Ge) by nearly three orders of magnitude, making it the most severely impacted device structure by TAT. The FS-iTFET, apart from having the largest area for line tunneling, also has the largest total heterojunction area, thereby accommodating the largest amount of Nit (Si/Ge) and increasing the influence of TAT. However, despite the significant increase in IOFF due to TAT, the FS-iTFET still outperforms the NS-TFET and NS-LTFET in subthreshold performance. As shown in Fig. 13b, the FS-iTFET maintains the maximum margin of SS relative to the drain current at Nit (Si/Ge) = 1012 cm−3, providing it with a competitive advantage in device operation.Fig. 13 a Transfer characteristics of the corresponding device structure with interface traps between heterojunctions, b Corresponding subthreshold swing (SS) versus drain current, c Impact of interface traps between heterojunctions on ION in different structures, d Impact of interface traps between heterojunctions on IOFF in different structures

Table 4 the ION, IOFF and SSAVG of the Proposed Device Structure Nit (Si/Ge) = 1012 (cm−3)

Stracture	FS-iTFET	NS-LTFET	NS-TFET	
ION (A/μm)	6.88 × 10–5	6.28 × 10–5	5.16 × 10–6	
IOFF (A/μm)	3.1 × 10–11	2.34 × 10–11	4.92 × 10–12	
ION / IOFF	2.22 × 106	2.68 × 106	1.05 × 106	
SSAVG (mV/dec)	33.2	47.5	57.6	

Overall, with the continuous advancements in future device manufacturing technologies and interface trap improvements, FS-iTFET has significant development potential. The performance comparisons of the three structures proposed in this paper with other literature in the field, as shown in Table 5 and Fig. 14, demonstrate that FS-iTFET exhibits excellent performance across various metrics, including ION / IOFF and SSAVG.Table 5 Performance comparison of this work and other TFETs

References	Structure	Material	VDD (V)	ION (A/μm)	IOFF (A/μm)	SSAVG (mV/dec)	ION / IOFF	
[18] 2023	Nanosheet-CTFET	SiGe/Si	0.5	8.1 × 10–5	8.11 × 10–10	33	105	
[19] 2020	Nanosheet-TFET	SiGe	0.5	1.76 × 10–4	3.72 × 10–12	29	4.73 × 107	
[20] 2022	Nanosheet-TFET	Si	0.5	1.7 × 10–6	1.69 × 10–15	24.6	109	
[21] 2021	Nanosheet-TFET	SiGe	0.7	5.32 × 10–8	5.3 × 10–12	82	104	
[25] 2022	Nanosheet-TFET	SiGe/Si	0.5	2 × 10–5	6 × 10–12	20	3.33 × 106	
This work	NS-TFET	Ge/Si	0.4	4.6 × 10–6	3.1 × 10–13	51	1.48 × 107	
This work	NS-LTFET	Ge/Si	0.4	3.29 × 10–5	2.18 × 10–12	41.2	1.51 × 107	
This work	FS-iTFET	Ge/Si	0.4	6.4 × 10–5	2.38 × 10–14	21	2.69 × 109	

Fig. 14 Benchmark comparison of the ION/IOFF ratio and average subthreshold swing (SSavg) of our devices with those proposed in other papers

Impact of subband quantum confinement effect to FS-iTFET

When the device size is reduced to the nanoscale, the Quantum Confinement Effect (QCE) significantly influences the current characteristics of the device. In Sentaurus TCAD, the Density-Gradient Model considers the spatial distribution of charge density altered by quantum effects [18]. This model is typically used in the design and analysis of semiconductor devices, especially at the nanoscale, where traditional classical physics models can no longer accurately describe charge behavior. However, as discussed in Sect. 2.2, the Density-Gradient Model neglects the bandgap widening caused by subbands under the quantum confinement effect [18], necessitating the use of the Schrödinger-Poisson model to address this issue.

According to Padilla et al. [10], changes in the bandgap significantly affect the behavior and characteristics of Tunnel Field-Effect Transistors (TFETs). Beneventi et al. [28] developed a method to simulate quantum confinement effects, resolving the incompatibility between the dynamic nonlocal path BTBT model's numerical solver and the Schrödinger-Poisson solver [24, 27, 28].

Following the simulation steps of Najam et al. [27], the overlap region between the gate and the source in FS-iTFET is defined as the quantization region, with the results shown in Fig. 15 and Table 6. Although Subband QCE significantly reduces the ION in FS-iTFET, it still maintains its excellent subthreshold characteristics. Benefiting from the stackable structure advantages of nanosheet, FS-iTFET is believed to possess outstanding potential for future development.Fig. 15 Impact of subband quantum confinement effect (QCE) on FS-iTFET: a Transfer characteristics of FS-iTFET with and without subband QCE, b Corresponding subthreshold swing (SS) versus drain current

Table 6 the ION, IOFF and SSAVG of FS-iTFET Nit (Si/Ge) = 1012 (cm−3)

FS-iTFET	w/o subband QCE	With subband QCE	
ION (A/μm)	6.88 × 10–5	1.76 × 10–5	
IOFF (A/μm)	3.1 × 10–11	8.36 × 10–13	
ION / IOFF	2.22 × 106	2.11 × 107	
SSAVG (mV/dec)	33.2	29.1	

Effect of sheet thickness on FS-iTFET

In this section, we investigate the changes in current characteristics considering Subband Quantum Confinement Effects (QCE), using the same methodology as in Sect. 3.8, as the source and channel thickness increases from 3 nm (6 nm body thickness) to 5 nm (10 nm body thickness). As depicted in Fig. 16 and Table 7, the FS-iTFET shows a better ION/IOFF ratio and subthreshold behavior at a source and channel thickness of 3 nm (6 nm body thickness) compared to 5 nm (10 nm body thickness). However, the magnitude of these differences is not significant, as the subthreshold swing (SS) remains within the sub-60 mV/dec range, with the drain current differing by only one order of magnitude.Fig. 16 Impact of channel/source thickness on FS-iTFET: a Transfer characteristics of FS-iTFET for different channel/source thicknesses, b Corresponding subthreshold swing (SS) versus drain current

Table 7 The ION, IOFF and SSavg of FS-iTFET with Body Thicknesses from 6 to 10 nm (Nit (Si/Ge) = 1012 (cm−3))

Source/Channel thickness	3 nm/3 nm (6 nm Body)	5 nm/5 nm (10 nm Body)	
ION (A/μm)	1.76 × 10–5	1.03 × 10–5	
IOFF (A/μm)	8.36 × 10–13	4.24 × 10–12	
ION / IOFF	2.11 × 107	2.43 × 106	
SSAVG (mV/dec)	29.1	36.5	

As the thickness decreases, quantum confinement effects become more pronounced, leading to subband splitting, which increases the energy gap in thinner semiconductor layers. This reduces the line tunneling rate and extends the tunneling distance, thereby decreasing the drive current. However, in the thinner layers, the vertical electric field is enhanced due to the reduced thickness, which increases the line tunneling rate, ultimately boosting the drive current. These competing effects—one decreasing and the other increasing the drive current—balance each other out, allowing the iTFET to maintain stable drive current and subthreshold performance even with reduced thickness. A similar balancing effect is observed at a 10 nm thickness, resulting in consistent stability.

In summary, the FS-iTFET exhibits highly stable subthreshold performance at ultra-scaled dimensions, maintaining excellent performance and good scalability at technology nodes below 5 nm and even smaller.

Conclusion

In this paper, we propose a novel FS-iTFET and conduct an in-depth exploration of its structural and performance advantages. The FS-iTFET employs a GAA structure and a complete line tunnel heterojunction channel. By introducing a metal–semiconductor Schottky junction in the inner source region to effectively induce carriers, the FS-iTFET achieves a steeper subthreshold swing and higher ION. Simulation results indicate that compared to conventional NS-TFETs and NS-LTFETs, the FS-iTFET demonstrates significant improvements in average subthreshold swing and ION/IOFF current ratio. Additionally, we delve into the impact of non-ideal effects such as TAT on the three different structures. Despite facing challenges in the manufacturing process, the FS-iTFET's superior performance and scaling potential in low-power and high-speed applications make it a promising candidate for future tunnel field-effect transistor technology. In conclusion, the FS-iTFET exhibits exceptional performance across multiple metrics, offering a new direction for the design of low-power, high-efficiency devices.

Author contributions

Professor Jyi-Tsong Lin conceptualized the study, developed the methodology, and played a significant role in writing, supervision, review, and editing. He initiated the research and provided valuable guidance throughout the project. Wei-Heng Tai, a student under his supervision, conducted the simulations, analyzed the data, and prepared the initial draft of the manuscript. All authors actively participated in reviewing and approving the final manuscript.

Funding

The funding was provided by Ministry of Science and Technology of Taiwan, R.O.C. (MOST109-2221-E-110-018-MY3).

Data availability

All the data are available from the corresponding author on reasonable request.

Declarations

Competing  interests

The authors declare no competing interests.

This work was supported in part by the Ministry of Science and Technology of Taiwan, R.O.C., under Contact MOST109-2221-E-110-018-MY3.

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
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