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Sci Rep
Sci Rep
Scientific Reports
2045-2322
Nature Publishing Group UK London

39223195
71436
10.1038/s41598-024-71436-w
Article
Cost-effective soft-switching ultra-high step-up DC–DC converter with high power density for DC microgrid application
Nadermohammadi Ali a.nadermohammadi1401@ms.tabrizu.ac.ir

1
Abolhassani Pouya 1
Seifi Ali 1
Zarrinehbafan Mohammadreza 1
Aghakhanlou Pouneh 1
Hosseini Seyed Hossein 12
Sabahi Mehran 1
1 https://ror.org/01papkj44 grid.412831.d 0000 0001 1172 3536 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, 51666-16471 Iran
2 grid.412132.7 0000 0004 0596 0713 Engineering Faculty, Near East University, 99138 Nicosia, Turkey
2 9 2024
2 9 2024
2024
14 2040713 5 2024
28 8 2024
© The Author(s) 2024
2024
https://creativecommons.org/licenses/by/4.0/ Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.
DC microgrids are integral to smart grids, enhancing grid reliability, power quality, and energy efficiency while enabling individual grid independence. They combine distributed and renewable energy sources, reducing overall energy consumption. High-gain DC–DC converters are crucial for elevating voltages from low-voltage DC sources like solar panels and wind turbines in DC microgrids. This paper introduces a non-isolated DC–DC converter designed to achieve ultra-high step-up (UHSU) voltage conversion utilizing a two-winding coupled inductor (CI). The propounded UHSU configuration achieves a substantial voltage increase by employing low duty cycles and a decreased turn ratio for the CI, resulting in a smaller core size. Moreover, this UHSU circuit incorporates soft-switching capabilities for both power switches and diodes, enhancing its efficiency. By keeping the voltage stress on the switches low, the design minimizes losses and improves overall efficiency. The operational modes are thoroughly analyzed, and comparisons with other topologies are presented to demonstrate the effectiveness of the proffered UHSU circuit. Finally, the performance of the UHSU circuit is validated through the construction and testing of a 150-W laboratory prototype operating at a switching frequency of 50 kHz, with Vin = 20 V and Vout = 300 V.

Subject terms

Electrical and electronic engineering
Energy grids and networks
issue-copyright-statement© Springer Nature Limited 2024
==== Body
pmcIntroduction

Power electronics play a crucial role in optimizing energy extraction from renewable sources. Illustrated in Fig. 1, a DC microgrid relies on high-gain DC–DC circuits to bridge between loads and sources, elevating low voltages (12–60 V) from batteries, solar PV, and fuel cells to higher DC voltages (200–300 V). Additionally, these converters regulate the DC-link voltage to the desired level. DC–DC converters in microgrid systems exhibit a wide range of power and output voltage, divided into three main categories. Low Power and Voltage Applications span from a few watts to tens of watts with output voltages between 12 and 48 V, commonly used to power sensors, small communication devices, low-demand devices like LED lighting, and to adjust the output of small residential fuel cells (24–48 V) to align with the microgrid's voltage. Medium Power and Voltage Applications range from hundreds of watts to a few kilowatts with output voltages between 48 and 120 V, suitable for integrating medium-sized renewable energy sources, managing batteries, and supporting medium-power household devices like lighting, small appliances, and HVAC systems. High Power and Voltage Applications encompass several kilowatts to tens of kilowatts with output voltages from 120 to 400 V or more, essential for large-scale energy storage, grid-connected renewable energy sources, and power distribution within the microgrid1–3. In modern DC microgrids, a blend of supercapacitors and high-gain converters is used due to the supercapacitors' high power density despite their low voltage rating. Additionally, high-gain converters are crucial for level three fast charging of electric vehicles. These high step-up DC–DC circuits are applied not only in renewable energy sources like photovoltaic systems and wind turbines but also in diverse fields such as industry, physical sciences, military, medical, transportation, and aerospace, where voltage boosting is needed4–12. However, inherent imperfections and resistance in the step-up circuitry can lead to increased conduction losses and issues with diode reverse recovery, particularly when duty cycles are very high4–6,13,14.Fig. 1 Schematic of DC microgrid.

Various methods for enhancing voltage have been explored by researchers in step-up DC–DC configurations to attain significant voltage gains without excessively large duty cycles. Comprehensive categorization of the voltage-boosting techniques is derived from five main sections: (1) multi-stage/level; (2) switched capacitor (charge pump); (3) voltage multiplier; (4) switched inductor and voltage lift; (5) magnetic coupling15–38.

Employing a multi-stage/level technique represents the initial approach to enhance the voltage gain of DC–DC structures, which encompasses three sections: cascade, interleave, and multilevel. However, these circuits suffer from complex control schemes, a plethora of elements, and high system costs. In recent works such as15,39–42, interleaved structures have been proffered, particularly suitable for photovoltaic (PV) applications due to their diminished input ripples. Switched capacitor (SC) is another prevalent voltage-boosting method based on the charge pump concept, as demonstrated in4, aiming to achieve high gain in DC–DC circuits. Nevertheless, SC-based circuits exhibit a significant drawback: they entail high instantaneous currents flowing through the capacitors, resulting in increased power losses and electromagnetic noise. On the other hand, the voltage multiplier technique has rendered configurations more efficient, with lower costs. These circuit topologies, relying on diodes and capacitors, are designed to achieve high voltage gain, as evidenced by works such as43,44. However, in studies like45,46, although the voltage multiplier method enables high voltage gain, the increased number of components escalates the cost and size of the circuit. Notably, the main drawback of voltage multiplier circuits lies in the high voltage stress experienced by elements. The Voltage Lift (VL) technique stands out as a widely employed method in DC–DC configurations to elevate the input voltage and attain high voltage gain47,48. VL involves charging a capacitor to a required voltage and leveraging it to boost the output voltage. This process can be further enhanced using additional capacitors, leading to configurations known as re-lift, triple-lift, and quadruple-lift structures. Switched inductor technique (SL), derived from both passive switched-inductor unit (PSL) and active switched-inductor unit (ASL), is another notable approach. ASL cells consist of active switches and inductors, while PSL cells comprise diodes and inductors. Studies such as49,50 have demonstrated that combining PSL and ASL structures can yield high voltage gain while keeping voltage stress across the power switches low. However, VL and SL techniques require additional passive elements and may not be appropriate for high-power applications. The magnetic coupling technique emerges as a promising solution for high step-up circuits. By utilizing CI in configurations, the number of components can be diminished compared to discrete inductors. CI-based converters offer an additional degree of freedom owing to their turn ratio, which can significantly increase voltage gain. Works such as15,16,24,26,27,51 have shown that adjusting the turns ratio among the primary, secondary, and tertiary windings of the CI can lead to remarkably high voltage gain in configurations.

This study presents a non-isolated DC–DC structure aimed at achieving ultra-high step-up voltage conversion through the use of a CI method. By adopting this approach, the voltage stress on the power switches is effectively diminished, allowing for the employment of low-voltage-rated switches with minimal on-resistance. As a result, conduction losses are minimized, ultimately contributing to improved efficiency.

The salient benefits of the propounded configuration are as:To manage the voltage gain of the configuration, the proffered design offers two adjustable parameters: the duty cycle of the power switches and the turns ratio of the CIs. This flexibility in design allows for effective control over the converter's voltage gain.

The voltage stress on the power switches is minimal, allowing for the use of low-voltage-rated switches with decreased on-resistance. This choice helps to mitigate conduction losses and ultimately enhances the total efficiency of the system.

The proffered configuration can produce a substantial output voltage with a minimal duty cycle, thereby decreasing the conduction loss of the switches.

Utilizing one core in the propounded structure reduces the size and cost of the circuit and enhances the power density.

Both power switches and three of the diodes have zero current switching (ZCS), which leads to enhanced efficiency.

Proposed converter and operation modes

The propounded configuration depicted in Fig. 2 illustrates the design of the presented configuration. This configuration includes two switches (S1 and S2), four capacitors (C1–C3 and CO), five diodes (D1–D5), and a coupled inductor with a two-winding configuration featuring a primary side winding (NP) and a secondary side winding (NS). Furthermore, the turns ratio of this coupled inductor is expressed as n = NS/NP, and the coupling coefficient is represented as k = Lm/(Lm + Lk). The propounded UHSU circuit, operating in continuous conduction mode (CCM), can be segmented into three subintervals, as demonstrated in Fig. 3. The primary waveforms of voltage and current for these components are illustrated in Fig. 4.Fig. 2 Power circuit of the propounded configuration.

Fig. 3 Equivalent circuits of the proffered circuit in boost mode (a) First switching subinterval, (b) Second switching subinterval, (c) Third switching subinterval.

Fig. 4 Main waveforms of the proffered circuit.

First switching subinterval

In this operational mode, both power switches are activated in zero-current-switching, while diodes D4 and D5 are forward-biased, and the remaining diodes are in a reverse-biased state. The magnetizing inductor Lm charges through the circuit path including Vin, C1, S1, Lm, and S2, resulting in a linear increase in iLm. At the same time, capacitor C2 charges via the loop consisting of C2, D4, and NS, and capacitor C3 charges through the circuit path comprising C3, NS, and D5. Throughout this time interval, the following relationships are maintained according to Kirchhoff's Voltage Law (KVL).1 VNs=nVLm

2 V1=VLm+VLk=VLmk

3 Vin=-VC1+V1

4 VNs=VC2

5 VC3=VNs

Second switching subinterval

In this interval, both power switches are turned off, and diodes D1 and D2 function under forward-biased conditions with ZCS conditions, while the remaining diodes are off. The magnetizing inductor's current decreases linearly. Capacitor C1 charges through the circuit loop involving C1, D1, Lm, and D2. According to KVL, the relationship governing this mode can be articulated as follows.6 V1=-VC1

Third switching subinterval

In this phase of operation, both power switches remain inactive, and diodes D1 and D2 continue conducting in a forward-biased state. Diode D3 enters conduction with ZCS conditions, while diodes D4 and D5 are in a reverse-biased state. The current in inductor Lm decreases steadily. Capacitor C1 charges through the circuit loop comprising C1, D1, Lm, and D2. Simultaneously, the output voltage VO is charged through the circuit path involving Vin, D1, Lm, D3, C2, NS, C3, and VO. According to KVL, the relationships governing this mode can be articulated as follows.7 Vin+VC1+VC2-VNs+VC3=VO

8 -V1=VC1

9 VO=-V1+Vin+VC2+VC3-VNs

Voltage gain calculation

The principle of volt-second equilibrium for the CI can be applied in the following way:10 VLmTS=0

11 V1TS=0

The capacitor voltages, obtained from Eqs. (12) and (13), are outlined below:12 VC1=DVin1-2D

13 VC2=VC3=Vinkn(1-D)1-2D

The formulated representation for the output voltage of the given setup is as follows:14 VO=Vin(1+2kn-D-nkD)1-2D

Neglecting the CI coefficient (especially for k = 1), the gain in output voltage should be expressed as:15 G=VOVin=1+2n-D-nD1-2D

Voltage stresses of semiconductors

The voltage across the circuit switches and diodes in the setup can be delineated as follows:16 VS1=DVin1-2D

17 VS2=(1-D)Vin1-2D

18 VD1=DVin1-2D

19 VD2=(1-D)Vin1-2D

20 VD3=(kn-D+1)Vin1-2D

21 VD4=VD5=knVin1-2D

Average currents of semiconductors

The average currents flowing through the power switches and diodes can be described as follows:22 IS1=IS2=(D+2n-Dn)IO1-2D

23 ID1=(1-D+2n-Dn)IO1-2D

24 ID2=(D+2n-Dn)IO1-2D

25 ID3=ID4=ID5=IO

Boundary condition

For the CCM operation of the suggested circuit, the minimum current of the coupled inductor must be more than zero. The minimum current of the CI and ΔiLm can be calculated as:26 ILm=(3n+1)IO1-2D

27 ΔILm=D×Vin×1+D1-2DLmfs

28 ILm,min=ILm-ΔILm2ILm,max=ILm+ΔILm2

29 Lm≥D×(1-2D+D)×(1-2D)×R2×(3n+1)×(1+2n-D-Dn)×fs

Normalized CI time constant can be expressed as:30 τ=2LmfsR

The boundary-normalized CI time constant can be described by employing (26), (27), (28) and (29).31 τB=D×(1-2D+D)×(1-2D)(3n+1)×(1+2n-D-Dn)

During continuous conduction mode, τ needs to surpass τB. Conversely, in discontinuous conduction mode (DCM), τB exceeds τ, while in boundary conduction mode (BCM), τ and τB must maintain equality.32 τ>τB;CCMτ<τB;DCMτ=τB;BCM

The depicted converter has the capability to function across different zones, contingent upon Eq. (32), as showcased in Fig. 5.Fig. 5 Boundary normalized inductor time constant versus duty cycle.

Efficiency calculation

In this section, calculations are performed to assess the conduction and switching losses of the proffered structure with the objective of optimizing its efficiency. To achieve this, factors such as the internal resistances of diodes (rD), switches (rS), inductors (rLm), capacitors (rC), as well as the forward voltage drop across diodes (VFD) and switches (VFS) are taken into account in determining power losses. Consequently, the conduction losses of switches and diodes are derived as follows:33 PCond,S1=DrsIO2D+2n-Dn22D-12-DVFsIOD+2n-Dn2D-1

34 PCond,S2=DrsIO2D+2n-Dn22D-12-DVFsIOD+2n-Dn2D-1

35 PCond,D1=-rD1IO2(D-1)D-2n+Dn-122D-12-VFD1IO(D-1)D-2n+Dn-12D-1

36 PCond,D2=-rD2IO2(D-1)D-2n+Dn22D-12-VFD2IO(D-1)D-2n+Dn2D-1

37 PCond,D3=-3IoD-1VFD3+IOrD35

38 PCond,D4=DIo(rD4Io+VFD4)

39 PCond,D5=DIo(rD5Io+VFD5)

The computation of switching losses for the power switches and diodes is carried out as follows:40 PSW,S1=D×IO×Vin×fs×toff×(D+2n-Dn)6×(2D-1)2

41 PSW,S2=-IO×Vin×fs×toff×(D-1)×(D+2n-Dn)6×(2D-1)2

42 PSW,D1=-D×Irr×Vin×fs×tb6×(2D-1)

43 PSW,D2=(D-1)×Irr×Vin×fs×tb6×(2D-1)

44 PSW,D3=-(n-D+1)×Irr×Vin×fs×tb6×(2D-1)

45 PSW,D4=-n×Irr×Vin×fs×tb6×(2D-1)

46 PSW,D5=-n×Irr×Vin×fs×tb6×(2D-1)

The overall power loss of the power switches and diodes, encompassing both switching and conduction losses, is represented as follows:47 PS,Tot=PCond,S1+PSW,S1+PCond,S2+PSW,S2

48 PD,Tot=PCond,D1,2,3,4,5+PSW,D1,2,3,4,5

The conduction losses associated with capacitors C1, C2, C3, and CO are determined as follows:49 PCond,C1=rC1IO2DD+2n-Dn22D-12-rC1IO2(D-1)D-2n+Dn22D-12

50 PCond,C2=rC2Io2(2D+3)5

51 PCond,C3=rC3Io2(2D+3)5

52 PCond,CO=12rCOIO25-7rCOIO2D5-2rCOIO2(D-1)D-2n+Dn252D-12

The overall power loss of the capacitors is represented as follows:53 PC,Tot=PCond,C1+PCond,C2+PCond,C3+PCond,CO

The expression for the conduction loss of the magnetizing inductor Lm is formulated as follows:54 PCond,Lm=rLmILm2=Io2rLm(3n+1)2(2D-1)2

The power loss associated with the core of the CI is denoted as follows:55 PC=kfsαBmβ

The power loss of the coupled inductor core (PC) is measured in W/kg. The coefficients utilized for the core, namely α, β, and k, are known as Steinmetz parameters, and they are often provided by producers for different core materials. The value of the α coefficient can vary between 1 and 2 for ferrite materials (1 ≤ α ≤ 2). based on Faraday's Law, this can be expressed as:56 VL=Ndφ(t)dt=NAcdB(t)dt

The core area, denoted as Ac, is specified by manufacturers for different types of magnetic cores. N represents the turn ratio of the CI. Consequently, the peak flux density, denoted as ΔB, for the CI can be determined as follows:57 ΔB=1NAc∫0DTsVindt=VinDTsNPAc=VinDNPAcfs

The core loss for the CI is represented as PCore = PCM, where M denotes the mass of the coupled inductor core. Hence, with Bm = ΔB/2 taken into account, the core loss is formulated as follows:58 PCore=kfsαVinD2NPAcfsβM

Referencing the book "Transformer and Inductor Design Handbook" authored by Colonel Wm. T. McLyman, the parameters employed to compute core losses include k = 5.597 × 10 − 4, α = 1.43, β = 2.85, Bm = 0.1 T, M = 0.088 kg, and fs = 50 kHz.

Therefore, the total power losses for the ultra-high step-up configuration are computed as follows:59 PLoss=PS,Tot+PD,Tot+PCond,Lm+PCore+PC,Tot

The efficiency of the proffered circuit (η) is determined as:60 η=POutPOut+PLoss

where POut represents the output power of the proposed configuration, defined as POut = VO2/RO.

By referencing Eqs. (33) to (60), the analytical efficiency of the propounded circuit can be derived, and the theoretical and experimental efficiencies of the proffered circuit versus output power are graphed in Fig. 6. Figure 7 illustrates the percentage distribution of power loss for each component type, while Fig. 8 provides a breakdown of power loss percentages specifically for conduction losses, switching losses, and core loss of the CI. As seen in Fig. 7, approximately half of the total power loss is attributed to the power switches, mainly due to their conduction losses. In Fig. 8, the switching losses of the diodes and switches, resulting from ZCS condition, are comparatively lower than both the conduction losses and the power loss of the CI core.Fig. 6 The theoretical and experimental efficiency of the proffered step-up configuration versus output power.

Fig. 7 Calculated power loss percentages for the components (PO = 150W, Vin = 20 V and Vo = 300 V).

Fig. 8 Calculated power loss percentages for conduction losses, switching losses, and core loss of the coupled inductor (PO = 150W, Vin = 20 V and Vo = 300 V).

Key parameter design guidance

Capacitors voltage ripple in boost mode

The capacitors' design characteristics are determined by averaging capacitor currents across all switching subintervals, considering capacitor voltages, duty cycles, allowable fluctuation range C%, and a prescribed switching frequency of 50 kHz. Consequently, the minimum values for capacitors C1 to CO can be computed as follows:61 C1≥IO×(2D-D-Dn)×(1-D)fs×Vin×D×xC1%

62 C2≥IO×D×(1-2D)fs×Vin×n(1-D)×xC2%

63 C3≥IO×D×(1-2D)fs×Vin×n(1-D)×xC3%

64 CO≥2IO×(1-D)×(1-2D)fs×Vin(1+2n-D-nD)×xCo%

Coupled inductor design

The design specifics of the CI rely on several factors, including the average currents flowing through it, the voltage applied across the CI throughout all switching intervals, the duty cycle, the allowable fluctuation range denoted as L%, and the frequency of switching. Consequently, the minimum value required for the magnetizing inductor can be formulated as follows:65 Lm≥Vin×(D-2D2+D2)fs×Io3n+1×xLm%

Number of primary and secondary winding turns of coupled inductor

The selected magnitude for the leakage inductor (Lk) is 3 µH. Consequently, the determination of the magnetizing inductor's value can be expressed utilizing the coupling coefficient of the CI as follows:66 Lm=3k×10-61-k

The magnetic core E42/21/15 has been selected for the CI. Consequently, according to the dimensions provided in the core datasheet, the air gaps of the core for the CI can be defined as follows:67 lg=LmILm2μ0Bm2AAirGap=3k×10-61-k×Io3n+11-2D2×4π×10-70.12×[(12.2+12.5)×15.2×10-6]

Through the utilization of Eq. (61), the count of primary winding turns for the CI can be obtained using the subsequent formula:68 NP≥Lm×lgμ0AAirGapEquivalent

The ratio of turns for the CI, denoted as n = NS/NP, establishes the count of secondary winding turns, which can be articulated as follows:69 NS=n×NP⇒NS=1.5×NP

Small-signal modeling

Each power semiconductor, the coupled inductor, and the capacitors are considered ideal in this analysis. The CI includes parasitic series resistors denoted as rLm, while the parasitic series resistors of capacitors are labeled as rC. Utilizing the state-space averaging method enables the derivation of both the average model and the small-signal model. System equations are formulated for all modes, and they are averaged over each commutation time, accounting for the time interval of each mode. Throughout all three switching subintervals, the system equations are expressed as follows:70 I˙LmV˙C1V˙C2V˙C3V˙CO=[Am]ILmVC1VC2VC3VCO+[Bm]Vin

where m = 1, 2, 3.

The control strategy for the presented converter employs the pole placement method, and the small signal model of the circuit is deduced from the state-space averaged model. Through the small signal modeling approach, state variables and control inputs are delineated into two components: fixed (X¯,D¯) and variable (x~,d~).71 X=X¯+x~D=D¯+d~

Applying this to the average model of the state space and disregarding their squared values, we derive the small signal model of the proffered structure.72 x~˙=Ax~+Bu~y=Cx~+Du~

where variable states (x~), control inputs (u~), and output signals (y) are described as follows:73 x~T=i~Lmv~C1v~C2v~C3v~CO

74 u~=d~

75 yT=ILm

According to the pole placement technique, the poles of the closed loop can be positioned at any suitable location given that the system is fully state-controllable. The controllability matrix of the proffered circuit is articulated as follows:76 ΦC=B⋮AB⋮A2B⋮⋯⋮An-1B

If the rank of ΦC equals 5, which is equivalent to the number of variable states (x~), then the system is considered fully controllable. Subsequently, two additional integral states are derived as follows:77 q˙(t)=r(t)-y(t)=r(t)-i~Lm(t)

With the inclusion of the new integral states, the state and output equations are reformulated as follows:78 x~˙(t)⋯q˙(t)=A⋮0⋯⋮⋯-C⋮0x~(t)⋯q(t)+B⋯0u~(t)+0⋯Ir(t)y(t)=C⋮0x~(t)⋯q(t)

In the equation provided, r(t) represents the input reference vector, defined as follows:79 r(t)=ILm,refT

According to Eq. (78), the new matrixes A¯ and B¯ are articulated as follows:80 A¯=A⋮0⋯⋮⋯-C⋮0,B¯=B⋯0

The controllability matrix for the system described in Eq. (78) can be defined as follows:81 Φ¯C=B⋮AΦC⋯⋮⋯0⋮-CΦC=B⋮A⋯⋮⋯0⋮-C⏟MI⋮0⋯⋮⋯0⋮ΦC

If ΦC is established to be complete-rank, the system mentioned in Eq. (78) is entirely controllable if the rank of the matrix M is n + m (where n and m represent the number of variable states (x~) and output signals (y), respectively). Therefore, there exists a matrix K calculated as:82 u~(t)=-Kx~(t)⋯q(t)=-Kx⋮Kqx~(t)⋯q(t)

where Kx and Kq expressed as follows:83 Kx=K11K12K13K14K15Kq=K11′

Substituting (82) in (78) the following equation is:84 x~˙(t)⋯q˙(t)=A-BKx⋮-BKq⋯⋮⋯-C⋮0x~(t)⋯q(t)+0⋯Ir(t)y(t)=C⋮0x~(t)⋯q(t)

To ensure suitable Gain Margin and Phase Margin values (GM ≥ 10 and 60 ≤ PM ≤ 80), the trial and error method is employed to determine the positions of the closed-loop poles. By following this approach, the bode plot of the control system for the proffered circuit is demonstrated in Fig. 9. As demonstrated in Fig. 9, the gain margin values for the inductor Lm exceed 10 (GM (iLm) > 10), and the phase margin for the control path (closed-loop) of iLm is 73.6953, which is deemed acceptable. Additionally, Figs. 10 and 11 depict the block diagram of the pole-placement control method and the current regulator loop of the coupled inductor, respectively.Fig. 9 Bode diagram for the transfer function of the inductor current.

Fig. 10 Block diagram of the pole-placement control technique.

Fig. 11 Current regulator loop of the coupled inductor.

Comparison study

In order to showcase the effectiveness of the proffered circuit, an examination is conducted to compare its performance with that of other configurations. Table 1 outlines the characteristics of the suggested converter alongside alternative configurations, covering aspects such as voltage gain, maximum stress on power switches and diodes, capability for soft switching, component count, nominal power, efficiency, and ability for common ground utilization.Table 1 Comparison between the propounded configuration and other circuits.

References	Voltage gain	Maximum voltage stress on switches	Maximum voltage stress on diodes	Soft switching capability	Number of *	T**/Power/Efficiency/Common ground	
S	D	C	L	CI	
Pro	1+2n-D-nD1-2D	(1-D)VO1+2n-D-nD	(n-D+1)VO1+2n-D-nD	Yes	2	5	4	0	1	12/150W/95.47%/Yes	
15	2n1-2D	12nVO	12VO	No	2	5	7	1	1	16/240W/92%/No	
16	2+n-D1-2D	VO2+n-D	(1+n)VO2+n-D	Yes	2	3	4	1	1	11/300W/96.8%/Yes	
17	3-2D1-2D	VO3-2D	VO3-2D	No	1	4	6	3	0	14/400W/91.25%/No	
18	1+D1-2D	VO1+D	VO1+D	No	1	3	4	2	0	10/100W/92.5%/No	
19	3-2D1-2D	VO3-2D	VO3-2D	No	1	4	5	2	0	12/150W/86%/Yes	
20	3-3D-2D2(1-2D)(1-D)	(1-D)VO3-3D-2D2	(2-3D)VO3-3D-2D2	No	2	4	5	3	0	14/200W/93.8%/No	
21	3-2D1-2D	VO3-2D	VO3-2D	No	1	5	6	2	0	14/130W/92%/Yes	
22	21-2D	VO2	VO	No	2	4	6	4	0	16/200W/93%/No	
23	3-D(1-D)2	DVO(1-D)2	VO1-D	No	1	6	6	3	0	16/100W/91%/Yes	
24	1+n+2nD-2nD2(1-D)2	VO1+n+2nD-2nD2	(1+n)VO1+n+2nD-2nD2	No	1	6	4	1	1	13/1014W/95.94%/Yes	
25	2-D1-2D	VO2-D	VO2-D	No	1	3	4	2	0	10/100W/92%/Yes	
26	2n+1+D(1-D)2	(1+D)VO2n+1+D	2nVO2n+1+D	Yes	2	5	5	1	1	14/280W/95.05%/Yes	
27	1+n(1-D)1-2D	VO1+n(1-D)	nVO1+n(1-D)	Yes	2	2	4	1	1	10/100W/95.6%/Yes	
28 BFSL	2-D(1-2D)(1-D)	(2-D)VO(1-D)	(2-D)VO(1-D)	No	1	5	5	3	0	14/200W/91.4%/Yes	
28 BCL	21-2D	2VO	2VO	No	1	4	4	3	0	12/200W/92.2%/Yes	
29	3-2D1-2D	VO3-2D	VO3-2D	No	1	4	5	2	0	12/150W/86%/Yes	
*Number of Switches/Diodes/Capacitors/Inductors/Coupled Inductors.

**Total number of components.

Table 1 presents a comprehensive overview of the converters discussed in references15–19. The focus of this paper revolves around the UHSU circuit, with voltage gain serving as the primary parameter for comparison. Figure 12 illustrates the variations in voltage gain across different duty cycles for the compared step-up configurations, with the depicted curves derived from the data expressed in Table 1. The results indicate that the suggested circuit outperforms other structures, particularly surpassing the UHSU configurations in references23,24,26. However, it's worth noting that the structures in references15,16 achieve a higher voltage gain per D > 0.4, albeit marginally higher than that of the proposed circuit. Nevertheless, the proposed converter demonstrates superiority across most factors examined in Table 1.Fig. 12 Voltage gain variations per different duty cycles for the compared step-up circuits with n = 1.5.

In Table 1, the second column presents the maximum voltage rating of the power switches. The variation of this parameter across different duty cycles is illustrated in Fig. 13. The graph in Fig. 13 highlights that the suggested circuit exhibits superior performance in terms of the maximum voltage stress experienced by the switches compared to other configurations. Notably, the voltage across the power switches is considerably low in the suggested circuit, enabling the selection of a smaller inductor for the propounded design.Fig. 13 Comparison of the maximum voltage stress on switches versus duty cycle (n = 1.5).

The third column in Table 1 provides information on the maximum voltage stress experienced by the diodes. Figure 14 displays the curve representing the maximum voltage stress on diodes across various duty cycles, considering a turns ratio (n) of 1.5. It is evident from Fig. 14 that the maximum voltage stress observed in the suggested configuration is lower compared to configurations presented in references16,18,22–24,27,28.Fig. 14 Comparison of the maximum voltage stress on diodes versus duty cycle (n = 1.5).

The fourth column of Table 1 indicates the presence of soft switching capability on semiconductor components. The proposed converter demonstrates ZCS turn-on, as illustrated in Fig. 5, which contributes to enhancing its efficiency. In contrast, configurations outlined in references15,17–25,28,29 lack soft switching capability on their semiconductor components.

The fifth column of Table 1 presents the count of switches, diodes, capacitors, inductors, and CIs. Unlike other configurations that typically employ at least two cores, the proposed converter utilizes only one core. This design choice enhances power density and reduces size due to the streamlined use of a single core. The total number of components is also noted in the subsequent column. In the suggested circuit, this count equals or is lower than most UHSU and high step-up circuits (equaling or being less than structures in15,17,19–24,26,28,29). However, it's important to note that the number of components alone may not fully capture the cost and power density metrics, as some converters with a higher component count may have lower costs and higher power densities due to the lower voltage and current ratings of the components. A cost analysis comparing the proposed converter with other structures is outlined in Table 2. Here, it's evident that the cost of the suggested converter is the most economical. The estimated costs of components were sourced from listings on platforms like AMAZON and EBAY, summarized succinctly in Table 2. The determination of the proffered circuit's volume and size distribution is detailed in Table 3. Notably, the CI constitutes a significant portion of the overall volume, followed closely by the capacitors, with the high-voltage side capacitor being the dominant contributor. In contrast, semiconductor devices make a comparatively minor contribution to the overall volume. Additionally, for comparative purposes, the power density is also provided in Table 4. The proposed converter achieves a theoretical power density of 150 W per 40,292.24 mm3, surpassing that of other circuits. It's worth noting that the cost and power density metrics were calculated for converters sharing component types. In the final column of Table 1, the power, efficiency, and common ground capability of the configurations are discussed. The propounded circuit is constructed for 150 W with an impressive efficiency of 95.47%, outperforming most other structures. Additionally, common ground capability between the input and output is highlighted as crucial, as configurations lacking this capability may be susceptible to electromagnetic interference noises affecting the circuits. Unlike converters found in15,17,18,20,22, the proffered structure possesses common ground capability. Comparative analysis reveals the superior voltage gain of the proposed configuration, along with reduced voltage stress on its power switches and diodes, all achieved at a low cost and with high power density. Moreover, owing to the low voltage stress on the power switch, the presented circuit necessitates a smaller inductor.Table 2 Cost comparison between the proffered configuration and other circuits.

References	Cost of switches	Cost of Diodes	Cost of Capacitors	Cost of Cores	Total Cost	
Pro	2 × 0.363$	2 × 0.476$

3 × 0.375$

	1 × 0.3145$, 2 × 0.4495$

1 × 0.799$

	1 × 2.7325$	7.548$	
15	2 × 1.235$	1 × 0.77$

4 × 0.689$

	1 × 0.988$, 2 × 0.599$

1 × 1.141$, 1 × 1.415$

2 × 0.799$

	2 × 5.05$	22.436$	
17	1 × 5.942$	4 × 1.35$	2 × 14.43$, 1 × 7.27$#3 × 6.70$	3 × 4.22$	80.232$	
18	The total cost, as calculated by the authors in18, is equal to: 7.95$	
29	1 × 1.18$	4 × 0.99$	5 × 0.988$	2 × 1.83$	13.74$	

Table 3 Power density of the propounded circuit.

Components	Specification	Volume	
Switches	IRF2807PbF

Length:23.74 mm

Width:10.67 mm

Thickness:4.83 mm

	2 × 1223.46 = 2446.92 mm3	
Diodes	BYV32E-200

Length:31 mm

Width:10.3 mm

Thickness:4.7 mm

SBR10U300CT

Length:29.15 mm

Width:10.31 mm

Thickness:4.67 mm

	(2 × 1500.71) + (3 × 1403.5)

 = 7211.92 mm3

	
Capacitors	C1

Diameter:6.3 mm

Height:11 mm

C2, C3

Diameter:13

Height:20

CO

Diameter:16

Height:25

	(342.90) + (3 × 2654.65)

 + (5026.55) = 13,333.4 mm3

	
Coupled Inductor	E42/21/15 core	17300 mm3	
	Total volume:	40,292.24 mm3	
	Power Density:	3.72 mW/mm3	

Table 4 Power density comparison between the proffered circuit and other configurations.

References	S.V* (mm3)	D.V* (mm3)	C.V* (mm3)	I.V* (mm3)	T.V* (mm3)	P.D* (mm3)	
Pro	2446.92	7211.92	13,333.4	17,300	40,292.24	150W/40,292.24 = 3.72 mW/mm3	
15	6174.88	9769.54	46,806.57	20,880	83,630.99	240W/83,630.99 = 2.86 mW/mm3	
17	3480.82	15,637.60	259,392	106,800	385,310.42	400W/385,310.42 = 1.03 mW/mm3	
29	2984.84	5955.44	47,516.6	23,000	79,456.88	150W/79,456.88 = 1.88 mW/mm3	
*S.V Switches Volume, *D.V Diodes volume, *C.V Capacitors Volume, *I.V Inductors Volume, *T.V Total Volume, *P.D Power Density.

Experimental results

To validate the theoretical analysis and actual execution of the proffered circuit, an experimental prototype with a power rating of 150 W is constructed. Table 5 outlines the key specifications of the propounded UHSU converter. Figure 15a depicts the measured output voltage and current, which are recorded at 290 V and 0.32 A, respectively. The theoretical output voltage predicted by Eq. (14) is approximately 300 V, closely matching the experimental result. This alignment validates the operation of the proffered circuit. Figure 15b,c display the voltage across capacitors C1, C2, and C3, measured at 38 V and 87 V, respectively. Theoretical calculations based on Eqs. (12) and (13) predict capacitor voltages of 40 V for C1 and 90 V for C2 and C3. Figure 16a presents the voltage across power switch S1 and the corresponding current through S1, which were measured at 37 V and 10 A, respectively. Additionally, ZCS on switch S1 is depicted in the same figure. In Fig. 16b, the voltage and current profiles of switch S2 are demonstrated, showing a voltage across S2 of 55 V and a current through S2 of 11 A. ZCS condition on switch S2 is also clearly visible in the same figure. Diode D1 enters conduction under ZCS condition, as shown in Fig. 16c. Voltage and current measurements across diode D1 indicate values of 38 V and 8 A, respectively. Similarly, diode D2 displays ZCS condition, with readings of 60 V and 8 A, as depicted in Fig. 17a. Under ZCS condition, diode D3 exhibits forward bias, registering a voltage of 180 V and a current of 1.7 A, as seen in Fig. 17b. The voltage and current profiles of diodes D4 and D5 mirror each other, as shown in Fig. 17c,d respectively, with measurements indicating 140 V and 1.4 A. Overall, Figs. 15, 16 and 17 collectively demonstrate that the experimental outcomes of the proffered converter closely correspond with the theoretical predictions derived from analysis, thus validating the converter's performance.Table 5 Component characteristic of the implemented circuit.

Parameters	Values	
Rated power (Po)	150 W	
Input voltage	20 V	
Output voltage	300 V	
Switching Frequency (fs)	50 kHz	
Turns Ratio n (NS/NP)	1.5	
Magnetizing Inductor (Lm)	500 µH	
Leakage Inductor (Lk)	3 µH	
Power Switches	IRF2807PbF	
Diodes (D1,D2)	BYV32E-200	
Diodes (D3,D4,D5)	SBR10U300CT	
Core type	E42/21/15	
Capacitor (C1)	22 µF/100 V	
Capacitors (C2, C3)	22 µF/250 V	
Capacitor (Co)	47 µF/450 V	

Fig. 15 The experimental waveforms of output port and capacitors, (a) voltage and current of the output port, (b) voltage across the capacitor C1, (c) voltage across the capacitors C2 and C3.

Fig. 16 The experimental waveforms of power switches and diode D1, (a) voltage and current of the power switch S1, (b) voltage and current of the power switch S2, (c) voltage and current of the diode D1.

Fig. 17 The experimental waveforms of diodes, (a) voltage and current of the diode D2, (b) voltage and current of the diode D3, (c) voltage and current of the diode D4, (d) voltage and current of the diode D5.

The proposed converter was tested under various load conditions and input values. In Fig. 18a, the output voltage of the converter initially registers around 290 V with a power output of about 150 W. When the load is suddenly altered and the output power is adjusted to 500 W, the output voltage remains relatively stable after brief transient fluctuations. The output voltage deviates only slightly from the reference value, demonstrating the stability of the closed-loop system in maintaining the output voltage close to the target. Figure 18b depicts the output voltage response when the input voltage suddenly drops from 20 to 16 V. It is evident from Fig. 18b that the output voltage shows minimal variation in response to the input change.Fig. 18 Dynamic response of the proposed converter, (a) step change of the load, (b) step change of the input voltage.

Conclusions

This paper introduces a non-isolated UHSU DC–DC circuit employing the CI method. The proffered UHSU configuration achieves an elevated voltage gain by increasing the turn ratio of the CI. Key merits of the proffered configuration include a high voltage gain with high efficiency, zero current switching of power switches and diodes during the ON-state, minimal voltage stress across semiconductor components, and the flexibility provided by two control parameters for adjusting the circuit's voltage gain (duty cycle and turns-ratio of the CIs). Additionally, the configuration is capable of generating high output voltage with a reduced duty cycle, thereby minimizing conduction losses in the switches. Furthermore, the proposed design offers high power density and cost-effectiveness. The suggested UHSU configuration offers a practical answer for converting low DC to high DC in DC microgrid application.

Author contributions

Conceptualization, A.N., P.A, A.S., M.Z., P.AG., S.H.H, and M.S.; methodology, A.N.; software, A.N., P.A, and A.S.; validation, A.N., S.H.H, and M.S.; investigation, A.N., P.A, A.S., M.Z., and P.AG.; resources, A.N., P.A, A.S., M.Z., and P.AG.; data curation, A.N.; writing—original draft preparation, A.N., P.A, and A.S.; supervision, S.H.H, and M.S.; Funding acquisition: A.N.; Visualization: A.N., P.A, A.S., M.Z., and P.AG.; writing—review and editing: A.N., P.A, and A.S.; project administration, A.N., S.H.H, and M.S.; Formal analysis: A.N. All authors have read and agreed to the published version of the manuscript.

Data availability

All data generated or analyzed during this study are included in this published article.

Competing interests

The authors declare no competing interests.

Publisher's note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
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